Continuous synchronization for multiple ADCs

Details Continuous synchronization for multiple ADCs Continuous synchronization for multiple ADCs

2008-10-13

2010-06-01

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C375S243000

Reexamination Certificate

active

07728753

ABSTRACT:
A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

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patent: 7215273 (2007-05-01), Waldner
patent: 7466251 (2008-12-01), Uchino

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