Continuous synchronization adjustment in a telecommunications sy

Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal

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370505, 370510, 370514, H04L 704

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active

059334681

ABSTRACT:
A continuous synchronization adjustment algorithm is described, which continuously synchronizes frames used in digital synchronous transmissions. By letting the receiver continuously adjust the assumed frame position, rather than adjusting only once per frame as conventionally done, a significant increase in bit error rate can be achieved. When an incorrect single sync bit is detected in a frame, thereafter during the rest of the frame, the single sync bit positions that would result from an advance or delay of the frame position (e.g., due to a bit slip in the frame) are checked. The frame position is then adjusted immediately, without waiting for the beginning of the next frame. Consequently, there is a significant decrease in the number of data bits that are interpreted incorrectly or disregarded. As such, the bit error rate resulting from the present continuous algorithm is significantly improved over that resulting from prior synchronization algorithms.

REFERENCES:
patent: 4232197 (1980-11-01), Acampora et al.
patent: 4592050 (1986-05-01), Bensadon
patent: 5084891 (1992-01-01), Ariyavisitakul et al.
Frame Synchronization Failure: Detection and Recovery by Arne Nilsson, Mark Perry and Mike Sutton, 1991 IEEE Transactions on Communications, vol. 39, No. 4, Apr. 1, 1991, New York, pp. 613-618, XP000241269.
EPO Search Report Form 1503, File RS 99163 US, Search Completed Sep. 10, 1997.

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