Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-01-21
2003-01-14
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S060000, C345S066000, C345S067000, C345S204000, C315S169100, C315S169200, C315S169400
Reexamination Certificate
active
06507327
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a plasma display panel (PDP) and a method of operating the display panel. More specifically, the present invention is related to apparatus and a method of concurrently addressing and sustaining the display panel.
BACKGROUND OF THE INVENTION
Plasma Display Panels (PDPs) offer promising technology for implementing large, flat video screens. A typical PDP may be formed by enclosing a gas, for example, a mixture of helium and neon between a transparent front panel and a back panel. Electrodes may be routed on the front panel and on the back panel and phosphors may be printed on either the front panel or the back panel. The electrodes are used to ionize the gas, forming a plasma which emits ultraviolet radiation. The ultraviolet radiation, in turn, causes the phosphors to emit visible light. Color displays are made by forming adjacent columns having red, green and blue phosphors, respectively.
A common type of PDP is the three-electrode pulsed Alternating Current (AC) device. In this configuration, each display row includes two parallel row electrodes, for example, on the inside surface of the back panel and each column includes one column electrode, for example, on the inside surface of the front panel. The row electrodes on the back panel may be covered with a dielectric layer so that no direct current (DC) flows between the electrodes when the plasma is formed. The electrodes on the front panel may also be covered with a dielectric layer.
Briefly, an AC plasma display operates in two phases or states, the writing phase (writing state) and the illumination phase (sustain state). In the writing phase of a given sub-field, data values are written into each pixel position of the display device one row at a time. The rows are selected one at a time by successively applying a scan potential to each row. At the same time, voltages are applied to the column electrodes to establish a relatively high potential between the column electrodes and the selected row electrode for pixels that are to be illuminated during the sustain state of the sub-field interval, and to establish a relatively low potential between the column electrodes and the selected row electrode for pixels that are not to be illuminated during the sustain state. The relatively high potential causes an electric charge to be deposited between the front and back panels, on the inside walls of the dielectric layers, at the respective pixel position. This electric charge is commonly known as a wall charge.
Thus, a pixel which will be bright has a wall charge written into it, and thus receives “ON” data. A pixel which will be dark does not have a wall charge written into it, and thus receives “OFF” data. In some implementations, the writing phase includes a preliminary erase step in which wall charges from the previous frame of data are erased.
After the wall charge has been written for each row of the display, the sustain state of the sub-field begins. During the sustain state a predetermined potential is applied in pulses between the two parallel row electrodes across the entire display. If a pixel position has a wall charge (“ON” data), the predetermined potential starts the plasma at that pixel position. If the pixel position does not have a wall charge (“OFF” data), the plasma does not start.
Each pixel of a plasma display panel is either turned on or turned off. Gray scale and different colors are implemented by dividing the field interval into multiple sub-fields, each comprising both an addressing phase and an illumination phase. The illumination phases of successive sub-fields have different lengths so that a given pixel illumination may be obtained by illuminating the pixel position only during some of the sub-fields. One method uses eight binary-weighted sub fields, such that the second sub-field being illuminated for twice as long as the first sub-field, the third sub-field being illuminated for twice as long as the second sub-field and so on. Using this method, monochrome images having 8-bit gray scale resolution and color images having 24-bits of color resolution may be displayed on the panel.
This high color resolution comes at a cost. In conventional PDPs, illumination is prohibited in the writing phase while rows are being written. Accordingly, if eight sub-fields are used, the display must be dark for eight addressing intervals during each frame interval. If illumination is attempted while rows are being written, crosstalk may occur as data voltages on the column electrodes may interfere with the discharge in unselected rows. Thus, adding sub-fields increases the gray scale and color resolution of the reproduced image but reduces its brightness. In some conventional display devices, about 50% of each frame time is taken up by the writing phases of the various sub-fields. Thus, a significant improvement to the art would be provided by a method for concurrently writing and illuminating a PDP.
SUMMARY OF THE INVENTION
The present invention provides a method of concurrently addressing and sustaining rows and columns in a plasma display panel (PDP) while not causing artifacts in non-addressed rows. Each PDP comprises a plurality of row electrode pairs, a plurality of column electrodes, and a plurality of pixels. A pixel is formed at the intersection of each row electrode pair and each column electrode. The method comprises the steps of sustaining the illumination of all pixels except those formed by the one row that is selected to receive new data. Pixels are addressed for illumination by providing data signals to the column electrodes and sustain signals to the display rows that are not being addressed, such that the data signals do not cause artifacts in the non-addressed rows.
According to one aspect of the invention, the voltage values for the binary one and binary zero data signals are selected to be symmetrical about one-half of the sustain voltage.
According to another aspect of the invention, the voltage values for the binary one and binary zero data signals are dynamically changed to temporally compensate for vertical crosstalk.
According to another aspect of the invention, the pixel values in the column are modified to compensate for vertical crosstalk in the column.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Ishii et al, “43.2 Driving of PDPs . . . Using a Grouped Address-While-Display Scheme”, SID 01 Digest, pp. 1134-1137.*
Kang et al, “43.1: A New 42-In. AC PDP Using MAoD II Driving Scheme”, SID 01 Digest, pp. 1130-1133.*
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Atherton James Harold
Kane Michael Gillis
Burke W. J.
Hjerpe Richard
Sarnoff Corporation
Tran Henry N.
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