Continuous error detection using duplicate core memory cells

Details Continuous error detection using duplicate core memory cells Continuous error detection using duplicate core memory cells

1992-12-18

1995-09-12

Beausoliel, Jr., Robert W.

Excavating

371 212, 371 671, 365201, G11C 700, G11C 2900, G06F 702, H04L 100

Patent

active

054504260

ABSTRACT:
A method of and apparatus for continuously checking a CMOS SRAM memory system. Each memory cell has a bistable circuit for retaining the state of the cell, along with a totally redundant bistable circuit. Added circuitry provides continuous comparing of the binary state of the bistable circuit and the redundant bistable circuit within the memory cell. This testing is performed at a low level within the memory cell eliminating the power dissipation and size requirements associated with additional drivers. An error line is shared amongst a number of memory cells. By continuously monitoring in this manner, the time of failure as well as the fact of failure can be determined.

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Clinton Kuo et al., Soft-Defect Detection (SDD) Technique for a High-Reliability CMOS SRAM, IEEE Journal of Solid-state Circuits, vol. 25, No. 1, Feb., 1990.

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