Excavating
Patent
1992-11-17
1995-07-18
Beausoliel, Jr., Robert W.
Excavating
371 492, G06F 1110
Patent
active
054348714
ABSTRACT:
A method of and apparatus for continuous parity checking within a CMOS SRAM memory system. Each cell has added circuitry which permits continuous reading of the binary state of the cell. The states of each cell are combined to produce a parity determination for a given data array. By continuously monitoring parity in this manner, the time of failure as well as the fact of failure can be determined.
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Johnson David C.
Purdham David M.
Beausoliel, Jr. Robert W.
Palys Joseph E.
Unisys Corporation
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