Electric heating – Heating devices – Combined with container – enclosure – or support for material...
Reexamination Certificate
2001-01-05
2002-12-17
Pelham, Joseph (Department: 3742)
Electric heating
Heating devices
Combined with container, enclosure, or support for material...
C219S411000, C219S413000, C228S102000, C228S180220
Reexamination Certificate
active
06495800
ABSTRACT:
BACKGROUND
“Wafer bumping” refers to a semiconductor packaging technology that prepares microchips for flip chip attachment onto an integrated circuit package or other electronic assembly. There are numerous different methods of wafer bumping, but the process typically involves placing tiny amounts of electrically conductive material onto the input/output pads of a wafer and then subjecting the wafer assembly with the electrically conductive material to a thermal process known as mass solder reflow. Controlling the wafer temperature is critically important to allow the solder to reflow while at the same time preventing damage to the wafer.
One prior art method of performing a solder reflow process is known in the industry as hot-plate technology. Hot-plate technology utilizes conduction, where the wafer is placed on a flat thermal mass precisely maintained at a given temperature. Conduction heating of the type employed in hot-plate technology is beneficial because the temperature of the wafer will not go higher than the temperature of the thermal mass (hot-plate) on which the wafer is sitting. Traditionally, hot-plate technology requires a system having multiple isolated hot plate stages and a means of moving the wafer to be reflowed from stage to stage to achieve proper heating.
There are several disadvantages to the prior art hot-plate type reflow system. First, because of their thermal mass, hot plates are slow to heat up and to cool down. Therefore, a lot of production time is lost when it is necessary to change set point temperature for a high temperature solder alloy to a lower temperature for a low temperature solder. Second, a pusher bar is typically used to push wafers from stage to stage. Spacing between pusher bars are established for a particular sized wafer, for example, eight-inch and twelve-inch wafers, etc. If the equipment is used with smaller wafers than it was designed for, production capacity is lost. Third, fluxes residues are formed from the wafers as they are heated, and the fluxes residues accumulate on plate surfaces. One source of flux is an organic acid that is put on a wafer to provide viscosity and to remove oxides on metal surface that inhibit good electrical connections. When passing through the various hot plates, the wafers get dirty from being pushed through the condensed fluxes, and have to be cleaned in an additional, costly step.
Fourth, commercially available hot plate equipment does not provide a controlled atmosphere surrounding the reflow and cooling areas that is capable of maintaining an inert atmosphere or reactive gas atmosphere that contains less than five parts per million oxygen molecules, and so allowing oxidation to occur. Fifth, the gas that is used in the prior art systems to control atmosphere causes wafer movement which makes in line processing using cassette to cassette loading equipment more difficult to use. Sixth, the condensed fluxes must frequently be manually removed from numerous parts of the hot-plate equipment causing significant lost production time and considerable expense.
SUMMARY OF THE INVENTION
The present invention is directed to a furnace for reflowing solder on a microchip. The furnace has a heating chamber with top, bottom, side, and end walls formed of sheets of porous insulation. The heating chamber has an entrance and an exit.
A first belt extends from a loading position through the heating chamber. A second belt is coupled to the first belt, the second belt extending through the exit of the heating chamber to an unloading position.
Within the heating chamber, below the first belt, infrared lamps are positioned. The infrared lamps heat the first belt, such that the first belt heats a microchip situated on the second belt.
In another embodiment the furnace has a housing with walls defining a heating chamber disposed between an entrance and an exit. Each wall of the housing includes a porous insulative inner panel and a non-porous outer panel.
The first conveyor moves an object from the loading position through the entrance of the heating chamber and through the heating chamber between the entrance and the exit. The second conveyor moves the object from the first conveyor through the exit of the heating chamber to an unloading position.
In an embodiment, the furnace has a pressurized gas inlet between the inner and outer panels to induce gas flow through the inner panel to the heating chamber. An area below the first conveyor is divided into stages transverse to the first conveyor. Each stage has at least one infrared lamp to heat the first conveyor.
REFERENCES:
patent: 2056207 (1936-10-01), Piazzoli, Jr.
patent: 2334865 (1943-11-01), Crawford
patent: 2674809 (1954-04-01), Meienhofer
patent: 2981819 (1961-04-01), Gregory
patent: 3415503 (1968-12-01), Beck
patent: 3436524 (1969-04-01), Pauls
patent: 3515854 (1970-06-01), Williams
patent: 3596125 (1971-07-01), Seigel
patent: 3603827 (1971-09-01), Degawa et al.
patent: 3619682 (1971-11-01), Lo et al.
patent: 3739215 (1973-06-01), Murai
patent: 3798061 (1974-03-01), Yamazaki
patent: 3818181 (1974-06-01), Benard
patent: 3836751 (1974-09-01), Anderson
patent: 3851200 (1974-11-01), Thomasson
patent: 3867660 (1975-02-01), Fohl
patent: 3882596 (1975-05-01), Kendziora et al.
patent: 4000407 (1976-12-01), Keller et al.
patent: 4025811 (1977-05-01), Van Nes
patent: 4100418 (1978-07-01), Brown, Jr.
patent: 4101424 (1978-07-01), Schooley et al.
patent: 4101759 (1978-07-01), Anthony et al.
patent: 4244285 (1981-01-01), Baker
patent: 4245613 (1981-01-01), Wells et al.
patent: 4323810 (1982-04-01), Horstmann
patent: 4389562 (1983-06-01), Chaudoir
patent: 4406944 (1983-09-01), Crain et al.
patent: 4435445 (1984-03-01), Allred et al.
patent: 4460821 (1984-07-01), Crain et al.
patent: 4477718 (1984-10-01), Crain et al.
patent: 4517448 (1985-05-01), Crain et al.
patent: 4558660 (1985-12-01), Nishizawa et al.
patent: 4820906 (1989-04-01), Stultz
patent: 4833301 (1989-05-01), Furtek
patent: 4856458 (1989-08-01), Yamazaki et al.
patent: 4876437 (1989-10-01), Kondo
patent: 4994705 (1991-02-01), Linder et al.
patent: 4997364 (1991-03-01), McGrath et al.
patent: 5008593 (1991-04-01), Schlie et al.
patent: 5094010 (1992-03-01), Jacobi et al.
patent: 5147130 (1992-09-01), Watanuki
patent: 5259546 (1993-11-01), Volk
patent: 5325601 (1994-07-01), Brownewell et al.
patent: 5340089 (1994-08-01), Heath et al.
patent: 5372781 (1994-12-01), Hallett et al.
patent: 5387546 (1995-02-01), Maeda et al.
patent: 5481087 (1996-01-01), Willemen
patent: 5504666 (1996-04-01), Carmichael
patent: 5505912 (1996-04-01), Hallett
patent: 5607609 (1997-03-01), Sakuyama et al.
patent: 5840600 (1998-11-01), Yamazaki et al.
patent: 5864119 (1999-01-01), Vogt et al.
patent: 5970384 (1999-10-01), Yamazaki et al.
patent: 6018144 (2000-01-01), Vogt et al.
patent: 0 108 314 (1984-05-01), None
patent: 4-262861 (1992-09-01), None
patent: WO 87/03077 (1987-05-01), None
De Rose-Juarez Selina
Garcia Luis Alejandro Rey
Phan Dienhung D.
Richert Carson T.
Szilagyi Andrei
Christie Parker & Hale LLP
Pelham Joseph
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