Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-12-14
2003-03-18
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S050000, C438S129000
Reexamination Certificate
active
06534841
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory structures, and is more particularly related to fabrication of an antifuse material in a memory structure.
BACKGROUND OF THE INVENTION
An antifuse structure can include a material which initially has a high resistance but which can be converted into a low resistance material by the application of a programming voltage. The programming voltage is in excess of a breakdown voltage of the high resistance material. The high resistance material is an electrically insulating antifuse layer which is sandwiched between a pair of electrically conductive layers. Each electrically conductive layer in the pair is generally considered an antifuse electrode of the antifuse structure. The high resistance material, also called an antifuse material or an antifuse layer, is non-conductive when manufactured but is caused to become permanently conductive by application of the programming voltage across the pair of electrically conductive layers.
When a programming current is applied through the antifuse layer across the pair of electrically conductive layers, an electrically conductive filament forms in the antifuse layer. The newly formed electrically conductive filament in the antifuse layer, which can be as narrow as several atoms in width, is effective as an electrical short of the two electrically conductive layers, thus programming the antifuse structure. Those antifuse structures that remain unprogrammed have no electrically conductive filament connecting their respective pair of electrically conductive layers.
Antifuse structures that are used in memory structures can be fabricated by integrated circuit technology. This fabrication can be directed to certain classes of IC chips such as field programmable gate arrays (FPGAs), programmable read-only memories (PROMs) and the like. FPGAs typically include a large number of logic elements, such as AND gates and OR gates, which can be selectively coupled to perform user designed functions. Programming a FPGA is generally accomplished by applying a programming voltage to selected antifuse structures thereby converting them into conductive interconnections.
During fabrication of an antifuse structure, the high resistance antifuse material serves the purpose of preventing unwanted electrical shorts from occurring between respective antifuse electrodes. This electrical insulation function of the antifuse material can be compromised in the fabrication process. The compromise can occur when patterning the antifuse material to form relatively short antifuse material segments across a wafer. Misaligned patterning of the antifuse material can result in antifuse electrodes in antifuse structures that make contact one with the other, and thus having an undesired electrical short. Misalignment can occur as design dimensions and process windows are subjected to increasingly higher scale integration in semiconductor die fabrication, such as where photolithographic resolution limits are approached.
When an unwanted short in an antifuse structure occurs, such as with a defect created during manufacturing, another antifuse structure must be used in place of the shorted antifuse structure. Even if redundancy is designed into memory structures, excessive electrical shorts cause nonfunctional memory cells, reduced fabrication yield, and increased costs to fabricate the memory structures. As such, it would be an advance in the art to reduce the incidence of unwanted electrical shorts between respective antifuse electrodes in antifuse structures during fabrication of memory structures.
It is desirable to fabricate memory structures with as few process steps and in as short of time in a clean room environment as practical. Short processing time in the clean room environment is desirable because operation and maintenance of the clean room environment for antifuse memory cell fabrication using semiconductor technology processes is time consuming and expensive. Fewer process steps in memory structure fabrication are desirable because each fabrication process step is both an expense and an opportunity to reduce yield. As such, it would be an advance in the art to reduce the time and processing required to fabricate memory structures.
SUMMARY OF THE INVENTION
In one embodiment, a memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.
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Eldredge Kenneth J.
Fricke Peter
Perner Frederick A
Van Brocklin Andrew L.
Wang S. Jonathan
Elms Richard
Hewlett--Packard Company
Smith Brad
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