Continuous amorphous silicon layer sensors using sealed...

Details Continuous amorphous silicon layer sensors using sealed... Continuous amorphous silicon layer sensors using sealed...

1999-12-28

2001-10-09

Ngô ;, Ngâ ;n V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S061000, C257S292000, C257S350000, C257S458000, C257S656000

Reexamination Certificate

active

06300648

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the structure of a high fill factor image array with a continuous sensor layer and its method of manufacture. More particularly, the present invention describes a high fill factor image array that reduces vertical leakage current by reducing contact injection current.
BACKGROUND OF THE INVENTION
A conventional image sensor array is typically formed from a plurality of photosensitive elements or pixels arranged in rows or columns.
FIG. 8
illustrates an example of a typical PIN (P+/Intrinsic/N+ layered) photosensitive element
10
used in the image sensor array.
Each photosensitive element
10
includes a contact pad
14
positioned over a substrate
11
. A photosensor island
12
of doped amorphous silicon (a-Si), includes a P+ doped region
24
and an N+ doped region
22
that covers contact pad
14
. Photons that enter photosensor island
12
generate electrons in the a-Si. An applied voltage generates an electric field between transparent upper conductive layer
16
of indium tin oxide (ITO) and contact pad
14
. The electric field moves the generated electrons to contact pad
14
. Passivation layer
18
separates transparent upper conductive layer
16
from substrate
11
except where the ITO contacts an upper surface of phosphor island
12
. Passivation layer
18
typically includes an oxynitride layer
26
and a polyamide layer
28
.
Conventional image arrays that use the photosensor element illustrated in
FIG. 8
include spaces between adjacent elements. These spaces do not detect light. A ratio of element areas that detect light to space areas occupied by the pixel is defined as a pixel fill factor. Method's of defining fill factor are described in an article entitled “High Efficiency X-Ray Imaging Using Amorphous Silicon Flat-Panel Arrays” by J. Rahn, F. Lemmi, J. P. Lu, P. Mei, R. B. Apte, and R. A. Street published in IEEE Trans. Nucl. Sci. (USA), IEEE Transactions on Nuclear Science (June 1999) vol.46, no.3, pt.2 p.
457-61 and hereby incorporated by reference.
High fill factor image arrays greatly improve the pixel fill factor such that an increased area of the sensor array detects light.
FIG. 9
illustrates a high fill factor image array
40
that uses a continuous P+ doped amorphous silicon layer
52
deposited over a continuous intrinsic amorphous silicon layer
50
. The continuous layers allow light detection across the entire sensor surface.
A voltage difference between upper electrode
54
and a plurality of source-drain metal contacts
44
on substrate
42
creates an electric field through amorphous silicon layers
50
. Upper electrode
54
is typically made of a transparent ITO while source-metal drain contacts
44
are made of an electrically conductive material such as a tri-layer TiW/A
1
/Cr. The electric field moves the generated electrons to contacts
44
. Each contact communicates with switching and processing circuits (not shown) that generate an image based on the charge on each contact.
Patterned back contact collection electrodes
46
coupled to each source-drain contact
44
increases the area of electron collection. An N+ doped amorphous silicon layer
48
is deposited over each source-drain contact
44
to form a PIN structure with continuous layers
50
,
52
. A conventional passivation layer, typically an approximately one micron thick oxynitride layer, serves as an insulator between adjacent mushroom electrodes.
One problem with conventional image arrays are leakage currents that arise due to material defects. Leakage currents include lateral leakage current between adjacent mushroom contacts and vertical or intrinsic leakage currents that occur along the direction of arrow
58
. Lateral leakage currents reduce image resolution. A typical 60×60 square micrometer of PIN sensor may include up to 0.3 pico-amps (pA) of lateral leakage current. A system for minimizing lateral leakage current is described in a patent application entitled Dual Dielectric Structure for Suppressing Lateral Leakage Current in High Fill Factor Arrays by Jeng Ping Lu, Ping Mei, Francesco Lemmi, Robert Street and James Boyce, Ser. No. (D/99215) 09/419,293 hereby incorporated by reference. a system for minimizing lateral leakage current is described in a patent application entitled dual dielectric structure for suppressing lateral leakage current in high fill factor arrays by jeng ping lu, ping mei, francesco lemmi, robert street and james boyce, Ser. No. 09/419,293, hereby incorporated by reference.
Vertical leakage current also degrades image quality by introducing noise. The introduced noise reduces image contrast and/or gray scale. A typical 60×60 square micrometer of a PIN sensor may include about 20 femto-amps (fA) of intrinsic leakage current at five volt contact voltages.
Thus a method and apparatus for reducing vertical leakage current is needed.
SUMMARY OF THE INVENTION
One problem with high fill factor image arrays is that vertical leakage currents reduce image contrast thereby degrading the quality of images output. One source of vertical leakage current is a contact injection current that results when a metal comes in contact with intrinsic amorphous silicon.
During fabrication of a typical back contact, a single mask is used to form both the metal back contact and an N+ doped amorphous silicon layer over the metal contact. However, the use of a single mask for both the N+ doped amorphous silicon layer and the metal back contact results in an edge of the metal being exposed to the intrinsic amorphous silicon. Despite the small size of the exposed area, it has been found that under certain reverse bias conditions, the area is sufficient to generate a large amount of vertical leakage current. In order to avoid vertical leakage current, one embodiment of the invention uses a second mask to generate a wider N+ amorphous silicon layer that seals in the metal portion of the back contact and prevents all direct contact between the intrinsic amorphous silicon layer and the metal back contact. An alternative embodiment of the invention replaces both the metal back contact and the N+ amorphous silicon layer with a single alternative material such as an N+ doped poly-silicon contact. Still a third embodiment of the invention retains the N+ amorphous silicon layer and replaces only the metal back contact with another conducting material that does not generate significant injection current when brought into contact with intrinsic amorphous silicon.


REFERENCES:
patent: 5682037 (1997-10-01), De Cesare et al.
patent: 6034725 (2000-03-01), Franklin et al.

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