Multiplex communications – Wide area network – Packet switching
Patent
1988-12-22
1989-10-03
Griffin, Robert L.
Multiplex communications
Wide area network
Packet switching
370 852, 3408255, H04J 324, H04J 302
Patent
active
048721638
ABSTRACT:
A contention mechanism is disclosed for a communication network that provides perfect scheduling to avoid collisions between packets from a cluster of M circuit boards connected to a communications bus. The contention mechanism includes a 2-phase contention procedure comprising a first phase priority contention phase, where boards with a highest priority and a real data packet to transmit proceed into a second contention phase, where a pointer is used to declare one of the remaining priority phase circuit boards as the overall winner to transmit its packet during a subsequent packet period. When no circuit board has a packet to transmit, all M circuit boards are declared as winners of the first priority phase, and a board is declared the winner on a distributed basis to transmit a "dead-space" packet over the bus. The real and dead-space packets can also be encoded and/or include a parity bit to ensure signal transitions sufficient to maintain a duty cycle required by A-C coupled devices connected in the network and also provide fault isolation.
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Follett David R.
Levy Michael P.
American Telephone and Telegraph Company
AT&T Bell Laboratories
Chin Wellington
Griffin Robert L.
Pfeifle Erwin W.
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