Content addressable semiconductor memory arrays

Details Content addressable semiconductor memory arrays Content addressable semiconductor memory arrays

1984-07-05

1988-12-27

Moffitt, James W.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365201, 365230, G11C 1504, G11C 1124

Patent

active

047945591

ABSTRACT:
A semiconductor memory circuit is arranged with an ordinary crosspoint row-column array of dynamic capacitor memory storage cells. Word serial content addressing is enabled by adding a separate combinational logic device, only one such device for each entire column bit line, typically comprising a comparator feeding a NAND gate to which masking data can be supplied.

REFERENCES:
patent: 4110842 (1978-08-01), Sarkissian et al.
patent: 4257110 (1981-03-01), Lamb et al.
patent: 4296475 (1981-10-01), Nederlof et al.
patent: 4404653 (1983-09-01), Ruhman et al.
W. A. Crofut et al, "Design Techniques of a Delay-Line Content-Addressed Memory," IEEE Transactions on Electronic Computers, vol. EC-15, No. 4, Aug. 1966, pp. 529-534.
T. Kohonen, Content-Addressable Memories, 1980, pp. 161-163.
T. Kohonen, Associative Memory, 1977, pp. 61-69.
R. M. Lea, "The Comparative Cost of Associative Memory," The Radio and Electronic Engineer, vol. 46, No. 10, Oct. 1976, pp. 487-496.

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