Content addressable memory with shifted enable signal

Details Content addressable memory with shifted enable signal Content addressable memory with shifted enable signal

2003-03-31

2004-06-08

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189110

Reexamination Certificate

active

06747886

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a content addressable memory.
2. Description of the Related Art
Content addressable memory (CAM), which provides access to stored data by input of data content instead of input of an address, can dramatically improve the performance of systems that must frequently retrieve or verify data. Some of the classic CAM applications include cache tagging, network switching and routing, data compression, and pattern recognition. Due to the increasing spread of mobile communications and computing, there is now interest in using CAM in a wide range of lightweight, low-power electronic devices, including devices powered by solar batteries.
Various types of CAM cells are known. One type is based on a static random-access memory (SRAM) cell connected between a pair of bit lines. The CAM cell adds a seek access circuit comprising four transistors connected in series between the same pair of bit lines, the two inner transistors being driven by the SRAM cell, the two outer transistors being driven by an enable signal. A match signal is output from a node located between the two inner transistors. The outer transistors speed up access by allowing the bit lines to be driven independently of the match signal line, and by allowing the match signal line to be precharged.
One problem in this type of CAM cell is that the on-resistance of the outer transistors in the seek access circuit slows the output of the match signal.
Another problem is leakage of subthreshold current through the seek access circuit. This problem becomes serious in devices that operate at low power supply voltages, such as the voltage supplied by a solar battery. The necessarily low threshold voltage of the transistors in such devices allows considerable subthreshold current to leak through. (Subthreshold current is current that leaks through a transistor when the gate-source voltage is below the threshold level and the transistor is turned off.) Besides causing needless current consumption, subthreshold leakage delays read and write access to the memory cells and reduces operating margins, raising the possibility of access errors.
SUMMARY OF THE INVENTION
An object of the present invention is to reduce the current consumption of a content addressable memory.
Another object of the invention is to increase the access speed of a content addressable memory.
Yet another object is to prevent access errors.
The invented content addressable memory uses conventional memory cells, each memory cell including a seek access circuit with four transistors connected in series between a pair of bit lines, the two inner transistors in the series being driven by a data storage circuit such as an SRAM cell connected to the bit lines, the outer two transistors functioning as enable transistors. A match signal is obtained from a node disposed between the two inner transistors.
The memory also includes a level shifting circuit that receives an enable signal and shifts at least one of the high and low logic levels of the enable signal, thereby widening the potential difference between the high and low logic levels. The shifted enable signal is used to drive the enable transistors in the seek access circuit in the memory cell.
Shifting the high logic level of the enable signal upward, above the supply voltage level, reduces the on-resistance of the enable transistors, thereby speeding up output of the match signal.
Shifting the low logic level of the enable signal downward, below the ground level, reduces the leakage of subthreshold current through the enable transistors, thereby reducing the current consumption of the memory cell, speeding up read and write access, and preventing access errors.


REFERENCES:
patent: 5285414 (1994-02-01), Yamauchi et al.

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