Content addressable memory with redundant repair function

Static information storage and retrieval – Addressing

Reexamination Certificate

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C365S230080, C365S189070

Reexamination Certificate

active

06917558

ABSTRACT:
A shift information latch circuit includes a plurality of latch portions provided corresponding to memory cell rows, respectively, and a fuse circuit transmitting fuse data produced corresponding to an address of a faulty memory cell row. The plurality of latch portion successively receive fuse data, and each transmit a shift control signal instructing a shift operation. In response to this shift control signal, a row decoder and a match line amplifier execute a shift operation for repairing the faulty memory cell row. In this structure, a decoder circuit decoding the address of the faulty memory cell row is not arranged so that a whole area of the circuits executing the shift operation is reduced, and the shift operation can be easily executed.

REFERENCES:
patent: 6034891 (2000-03-01), Norman
patent: 6042241 (2000-03-01), Lengyel
patent: 6441811 (2002-08-01), Sawada et al.

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