Content addressable memory with reduced transient current

Details Content addressable memory with reduced transient current Content addressable memory with reduced transient current

1999-08-18

2001-05-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189050, C365S189070, C365S194000

Reexamination Certificate

active

06240000

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to content addressable memories (CAMs) and more particularly to approaches to reducing current transients in a CAM.
BACKGROUND OF THE INVENTION
Due to the increased prevalence of information networks, including the Internet, content addressable memories (CAMs) continue to proliferate. CAMs, also referred to as “associative memories,” can provide rapid matching functions that are often needed in routers and network switches to process network packets. As just one example, a router can use a matching function to match the destination of an incoming packet with a “forwarding” table. The forwarding table can provide “nexthop” information that can allow the incoming packet to be transmitted to its final destination, or to another node on the way to its final destination. Of course, CAMs can also be used for applications other than network hardware.
A typical CAM can store a number of data values in a CAM cell array. In a compare (i.e., match) operation, the data values can be compared to a comparand value (also referred to as a “search key”). A data value that matches the comparand value can result in the generations of a match indication.
In many CAMs, match indications for data values are provided by conductive match lines. In some arrangements, the match lines can be precharged to a predetermined voltage prior to a compare operation. Subsequently, when a compare operation takes place, the match line(s) corresponding to a mismatch between a comparand value and a data value can be discharged (or charged) to a different voltage level. The different voltage level can indicate a match condition. Accordingly, as multiple match lines are charged and discharged, current is consumed by a CAM. Current consumption can be considerable for larger density CAMs. For example, a 64-bit×16K CAM can precharge over 16,000 match lines at essentially the same time.
Other structures within a CAM can also consume current. As just one example, in addition to match lines, a CAM can include comparand lines that can carry the comparand value bits to a CAM cell array. In some arrangements, the comparand lines are complementary comparand lines that are first precharged/equalized to a precharge potential or predischarged to a predischarge potential, usually zero volts. The comparand values can then be driven with the comparand value. Thus, the operation of comparand lines can also consume current.
As CAM sizes increase, the size of match lines and/or comparand lines can also increase. Thus, a compare operation in a conventional CAM can result in substantial current draws on a CAM power supply (current transient peaks). Such current draws can result in a voltage drop on the CAM power supply (a temporary “collapse” in the power supply voltage). A drop in a CAM power supply may have a variety of adverse effects on the operation of the CAM. As just a two examples, as a power supply voltage drops, various circuit nodes are slower to charge and/or device impedance can increase. Thus, the operation of the CAM can slow down until the CAM power supply returns to its previous level (“recovers”). Because CAM memory cells can include volatile storage devices, a drop in the CAM power supply voltage can result in the corruption of stored data. In one particular example, static volatile storage devices, such as latches and/or register circuits, can have stored logic values reversed (“flipped”) if a power supply dip is sufficiently severe.
It would be desirable to arrive at some way of operating a CAM that can reduce current transient peaks.
CAM devices can be synchronous and/or asynchronous. A synchronous CAM can perform matching functions on applied comparand values according to a periodic timing signal (such as a system clock, as one example). An asynchronous CAM can perform matching functions on applied comparand value according a non-periodic timing signal (such as an applied comparand value, as just one example).
It is often desirable for synchronous CAMs to operate according to particular timing specifications. As just one example, it is desirable to have a CAM that can receive a comparand value on a certain clock edge, and then provide a compare result a predetermined number of clock cycles later. Such configurations can allow comparand values to be applied every clock cycle, resulting in the generation of compare results every clock cycle.
CAMs can include “binary” CAMs in which a multi-bit comparand value must match with every bit of a data value to generate a match indication. CAMs can also include “ternary” CAMs in which multi-bit comparand values can be compared with “maskable” data values. A maskable data value can have one or more bits that can be masked from the compare operation. A masked bit will not generate a mismatch indication even if the masked data value bit is different than the corresponding comparand value bit. Thus, a match indication can include a binary or a ternary match indication, according to the type of CAM.
CAMs can receive comparand and/or data values by way of data buses. Systems that utilize electronic devices like CAMs, can often include components that process data values having bit widths that are larger than available bus sizes. Accordingly, it would be desirable to provide a CAM that can receive comparand values by way of a bus having a width smaller than a comparand value.
A conventional CAM will now be described to better understand the various disclosed embodiments of the present invention.
Referring now to
FIG. 12
, one example of a conventional CAM is set forth in a block schematic diagram. The conventional CAM is designated by the general reference character
1200
, and is shown to include a number of CAM cells
1202
, coupled to match lines (MATCH
0
to MATCHz) and complementary comparand value lines
1204
.
In a compare operation, initially, match lines (MATCH
0
to MATCHz) can be precharged to a first potential (a logic high, for example) by precharge circuits
1206
. Precharge circuits
1206
can be activated by a match line precharge signal MATCH_PRECH. Such an operation can consume a relatively large amount of current.
In addition, the complementary comparand value lines
1204
can be predischarged and/or equalized by predischarge/equalization circuits
1208
. Predischarge/equalization circuits
1208
can be activated by a compare line predischarge signal CMP_PREDISCH. This operation can also consume some current.
Once the match lines (MATCH
0
to MATCHZ) are precharged and the complementary comparand value lines
1204
are predischarged and/or equalized, a comparand value can be applied by way of complementary comparand value lines
1204
. In the event there is no match (a mismatch condition) between a data value stored in a row of CAM cells
1202
and the applied comparand value, the corresponding match line (MATCH
0
to MATCHz) can be discharged. In the event there is a match condition between a data value stored in a row of CAM cells
1202
and the applied comparand value, the corresponding match line (MATCH
0
to MATCHZ) can remain precharged, and thereby provide a match indication.
SUMMARY OF THE INVENTION
According to disclosed embodiments, a content addressable memory (CAM) can distribute a single compare operation into a number of sequential compare operations, thereby reducing the magnitude of current transients.
According to one aspect of the embodiments, the CAM can operate in synchronism with a periodic clock signal, and the compare operations can be distributed over a clock signal period.
According to another aspect of the embodiments, a CAM can include a segmented mode of operation in which a comparand value is divided into comparand portions. Data values stored by the CAM are divided into corresponding data value portions. Sequential compare operations can compare comparand portions to corresponding data value portions.
According to another aspect of the embodiments, a CAM can include a segmented mode of operation. If a compare operation indicates a mismatch between a comparand portion and d

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