Content addressable memory with reduced test time

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

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C365S201000, C711S108000

Reexamination Certificate

active

11256066

ABSTRACT:
A CAM device having internal circuitry to reduce test time through parallel test setup and parallel pass/fail result generation. A plurality of match results is generated in parallel within a plurality of CAM blocks of the CAM device in response to a search instruction, each match result including a block flag signal that indicates whether a match was detected within a corresponding one of the CAM blocks and a block index that indicates a location of an entry within the one of the CAM blocks. The block index and block flag signal of a highest priority one of the match results is output from the CAM device if an operating mode value indicates a first operating mode, and the block flag signals of the plurality of match results is output from the CAM device if the operating mode value indicates a test operating mode.

REFERENCES:
patent: 6418042 (2002-07-01), Srinivasan et al.
patent: 6539455 (2003-03-01), Khanna et al.
patent: 6564289 (2003-05-01), Srinivasan et al.
patent: 6609222 (2003-08-01), Gupta et al.
patent: 6934795 (2005-08-01), Nataraj et al.
patent: 6934796 (2005-08-01), Pereira et al.
patent: 2004/0128441 (2004-07-01), Regev et al.

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