Content addressable memory with power reduction technique

Details Content addressable memory with power reduction technique Content addressable memory with power reduction technique

2001-09-21

2003-11-11

Le, Thong Quoc (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S190000

Reexamination Certificate

active

06646899

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of content addressable memories and, more particularly, to power reduction techniques in content addressable memories.
2. Description of the Related Art
Content addressable memories (CAMs) have a variety of uses in integrated circuits. Generally, a CAM is a memory comprising a plurality of entries, and each entry is configured to store a value. An input value to the CAM is compared to the values stored in the entries, and an indication of which entry (or entries) is storing a value equal to the input value is provided as an output of the CAM. If an entry is storing a value equal to the input value, the input value is said to be a hit in the CAM.
One exemplary use of a CAM is in a translation lookaside buffer (TLB) in a processor. The CAM may be used to store a portion of the virtual address (that portion which is translated from the virtual address to the physical address, also referred to as the virtual page number or VPN). A corresponding random access memory (RAM) may be included which stores the corresponding portion of the physical address (also referred to as the page frame number (PFN)) for each virtual address in the CAM. The indication of a hit in a particular entry of the CAM may be used to read the physical address from the corresponding entry of the RAM. Many other uses for CAMs are found both in processors and in other types of integrated circuits.
Generally, CAM memories have a dynamic OR-based exclusive NOR structure. In such a structure, the bits of the value in a given CAM entry are exclusive NORed with corresponding bits of input value to be compared. The resulting output signals are ORed together to produce the compare result for the entry. If any bit in the entry miscompares, the OR result is a logical one (miss), and if all bits are equal the OR result is a logical zero (hit). In a dynamic OR, the output is precharged to logical zero and transitions to a logical one if any inputs are a logical one. Accordingly, each entry for which a miss is detected consumes power in generating the result for such a structure.
SUMMARY OF THE INVENTION
In one embodiment, a CAM is provided which includes a plurality of CAM cells and a circuit coupled to the plurality of CAM cells. Each of the plurality of CAM cells is configured to store a different bit of a value and is coupled to receive a corresponding bit of an input value. Each CAM cell is configured to generate an output indicating if the corresponding input bit and the bit stored in that CAM cell match. The circuit is coupled to receive the outputs from the plurality of CAM cells and is configured to logically AND the outputs to generate a hit output. The hit output indicates whether or not the input value matches the stored value.
In another embodiment, a pair of compare line generator circuits are provided. One of the compare line generator circuits is coupled to receive a clock signal and a data signal, and is configured to generate a first pulse responsive to the clock signal and the data signal. The other of the compare line generator circuits is coupled to receive the clock signal and a complement of the data signal, and is configured to generate a second pulse responsive to the clock signal and the complement of the data signal. In one implementation, the first and second pulses may be provided to a CAM cell for selection as a compare output of the CAM cell dependent of the value stored in the CAM cell. In one embodiment, the compare line generator circuits are further coupled to receive a mask input and are configured to generate both the first and the second pulses responsive to the clock signal and the mask input.
In yet another embodiment, a CAM is contemplated including a circuit configure to generate a pulse indicating a hit in an entry of the CAM. The CAM further includes a latch circuit coupled to receive the pulse, a first clock signal, and a second clock signal. The latch is configured to capture the pulse responsive to the first clock signal and is configured to clear responsive to the second clock signal. In one implementation, the output of the latch is used as a word line to a RAM. In one embodiment, the second clock signal is delayed from a third clock signal by an amount which provides a minimum width of the word line in a phase of the third clock signal in which the RAM is read.
In still another embodiment, a first CAM and a second CAM are provided. The first CAM may store a value in each entry and may further store a compare result of the value and an input value to the first CAM. The second CAM may include entries corresponding to the entries in the first CAM, and each entry may be coupled to receive the indication of the compare result from the corresponding entry of the first CAM and is configured to generate a second compare result which includes the first compare result. In one implementation, the first and second CAMs may be included in a translation lookaside buffer, with the first CAM storing an address space identifier and the second CAM storing a virtual address (or portion thereof).


REFERENCES:
patent: 5598115 (1997-01-01), Holst
patent: 5754463 (1998-05-01), Henstrom et al.
patent: 6166939 (2000-12-01), Nataraj et al.
patent: 6175514 (2001-01-01), Henderson et al.
patent: 6266263 (2001-07-01), Lien et al.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum 2000, Jun. 13, 2000, 15 pages.
Jim Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
Tom R. Halfhill, “SiByte Reveals 64-Bit Core For NPUs; Independent MIPS64 Design Combines Low Power, High Performance,” Microdesign Resources, Jun. 2000, Microprocessor Report, 4 pages.
SiByte, Letter from Anu Sundaresan, May 18, 2000, 1 page.

Affiliated with

Also associated with

Rating

Content addressable memory with power reduction technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Content addressable memory with power reduction technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Content addressable memory with power reduction technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3166670