Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2001-03-01
2002-06-04
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189070, C365S203000
Reexamination Certificate
active
06400594
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology for reducing the power consumption in a content addressable memory device.
2. Description of the Related Art
FIG. 17
shows one example of a content addressable memory (hereinafter, referred to as a CAM) device. In the figure, a CAM device
118
includes a CAM cell array
120
having an N bit width×M word construction, a decoder
122
, a bit line control circuit
124
, a match detecting circuit
126
, a flag generator
128
, and a priority encoder
130
. Although not shown, the bit line control circuit
124
includes a bit line precharge circuit, a bit line driver, a sense amplifier, a search data register, a mask register, and the like.
In the CAM device
118
, storage data is read and written in the same manner as in a normal RAM. That is, when data is written, the decoder
122
selects a word WL corresponding to an address ADR. The bit line driver drives data DATA as storage data on a bit line BIT and negated data /DATA (the negated signal of data DATA) as storage data on a bit bar line /BIT. The driven data is written in the word WL corresponding to the address ADR.
When data is read, the decoder
122
selects the word WL corresponding to the address ADR. This allows DATA (the storage data) to be read on the bit line and the /DATA to be read on the bit bar line. Thereafter, the sense amplifier detects the read data, and the storage data stored in the word WL corresponding to the address ADR is read as DATA.
Match searching of search data is performed on storage data as follows. After storage data is written to each word of the CAM cell array
120
in the above-described manner, the search data is input as DATA, instructing the start of search. By loading the search data in the search data register, and then driving the search data DATA on the bit line BIT and its negated signal /DATA on the bit bar line /BIT, match searching of the search data is performed on the storage data of every word.
The match detecting circuit
126
corresponding to each word via a match line ML detects a search result. The detected data is input to the flag generator
128
and the priority encoder
130
. The flag generator
128
outputs, as a flag, one state of “no matching”, “single matching”, and “multiple matching” in accordance with the result. When matching occurs, the priority encoder
130
outputs the memory address of the matched word having a predetermined high priority as a high priority hit address (HHA).
Match searching of the CAM device
118
is described in more detail by giving examples of the CAM cell shown in
FIGS. 18A
to
18
C. The CAM cells shown in these figures are constructed using a SRAM (static random access memory).
In a CAM cell
132
shown in
FIG. 18A
, match searching is performed by setting the bit line BIT and the bit bar line /BIT to LOW, turning off an N-type MOS (Metal Oxide Semiconductor) transistor
138
(hereinafter, referred to as an NMOS) which is connected between the match line ML and the ground, precharging the potential of the match line ML to the potential of a power source, and driving the search data DATA on the bit line BIT and the search data bar /DATA on the bit bar line /BIT.
When the storage data and the search data match, the gate of the NMOS
138
is maintained at LOW via either an NMOS
134
or an NMOS
136
which is turned on in accordance with the storage data. Therefore, the match line ML remains precharged. However, when the storage data and the search data do not match, a HIGH level signal is input into the gate of the NMOS
138
via either the NMOS
134
or the NMOS
136
which is turned on. Since this turns on the NMOS
138
, the match line ML is discharged.
In a CAM cell
140
shown in
FIG. 18B
, match searching is performed by setting the bit line BIT and the bit bar line /BIT to LOW, turning off an NMOS
146
and an NMOS
148
, which are connected to the ground, precharging the potential of the match line ML to the potential of the power source, and then driving the search data DATA on the bit line BIT and the search data bar /DATA on the bit bar line /BIT.
When the storage data and the search data match, either an NMOS
142
or the NMOS
146
is turned off and either an NMOS
144
or the NMOS
148
is turned off in which a pair of the NMOSs
142
and
146
and a pair of the NMOSs
144
and
148
are individually connected in series between the match line ML and the ground. Accordingly, the match line ML remains precharged. When the storage data and the search data do not match, both the NMOS
142
and the NMOS
146
or both the NMOS
144
and the NMOS
148
are turned on. This allows the match line ML to be discharged via the NMOS transistors, both of which are turned on.
In a CAM cell
150
shown in
FIG. 18C
, match searching is performed by setting the bit line BIT and the bit bar line /BIT to HIGH, turning off two P-type MOS transistors (hereinafter, referred to as a PMOS)
156
and
158
, which are connected to the match line ML, discharging the match line ML to the ground potential, and then driving the search data DATA on the bit line BIT and the search data bar /DATA on the bit bar line /BIT.
When the storage data and the search data match, either a PMOS
152
or the PMOS
156
is turned off and either a PMOS
154
or the PMOS
158
is turned off in which a pair of the PMOSs
152
and
156
and a pair of the PMOSs
154
and
158
are individually connected in series between the match line ML and the power source. Accordingly, the match line ML remains discharged. On the other hand, when the storage data and the search data do not match, both the PMOS
152
and the PMOS
156
or both PMOS
154
and the PMOS
158
are turned on. This allows the match line ML to be charged via the PMOS transistors both of which are turned on.
In the case of the CAM device
118
shown in
FIG. 17
, one word is constructed using N CAM cells, the CAM cells which constitute the same word are connected to the match line ML. Accordingly, the match line ML is maintained at a standby level only when matching is detected on all of the CAM cells constituting the one word. When mismatching is detected in any of the CAM cells constituting the one word, the match line ML is discharged from the standby potential.
The CAM cells
132
,
140
, and
150
shown in
FIGS. 18A
to
18
C are mismatch-detecting types. When mismatching occurs, the match line ML is discharged/charged so that the logical level of the match line ML becomes the opposite logical level of the precharge potential. However, since storage data of most words are mismatched, when the mismatch-detecting type CAM cells shown in
FIGS. 18A
to
18
C are used, the potentials of most match lines ML are discharged/charged to the opposite logical level of the precharge potential. This means that the potentials of most match lines ML swing from the power source potential to the ground potential every searching cycle.
In the case of each of the CAM cells
132
and
140
in
FIGS. 18A and 18B
, respectively, the following steps must be executed in order to perform match searching. After normal storage data is read or written, a bit line pair of the bit line BIT and the bit bar line /BIT is precharged to the power source potential during the standby time. During match searching, the bit line pair is discharged to the ground potential and then the match line ML is precharged to the power source potential. Thereafter, either the bit line BIT or the bit bar line /BIT is driven to the power source potential again in accordance with the search data.
That is, in order to precharge the potential of the match line ML, the bit line pair of BIT and /BIT must be temporarily discharged to the ground potential. The amount of current required for these precharging and discharging is dissipated. On the other hand, in the case of the CAM cell
150
in
FIG. 18C
, the match line ML is discharged, and then either BIT or /BIT of the bit line pair which is precharged to the power source potential is discharged to the g
Hata Ryuichi
Iwasaki Hideaki
Kanazawa Naoki
Yoneda Masato
Elms Richard
Kawasaki Steel Corporation
Nguyen Hien
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