Content addressable memory system employing charge coupled devic

Details Content addressable memory system employing charge coupled devic Content addressable memory system employing charge coupled devic

1975-04-01

1976-12-14

Fears, Terrell W.

Communications: electrical

Digital comparator systems

3401725, G11C 1500

Patent

active

039978826

ABSTRACT:
A content addressable memory system for accessing blocks of data stored in circular charge coupled shift registers in response to a tag word presented to a directory unit comprising circular charge coupled shift registers. The memory includes clocking and logic circuitry for providing selective, high speed clocking of blocks and directory unit registers for both read and write operations. Additional logic facilitates masked directory searches at selective clock rates. Automatic synchronization of fast and slow clocked registers is provided by a counter of predetermined count corresponding to the formula N/(1-H) where H is the number of bits per circular register and H equals the ratio of slow to fast shift rates. A use bit register in the directory unit and a bookkeeping loop register in each module further aid in synchronization of the memory operation.

REFERENCES:
patent: 3733589 (1973-05-01), Thompson
patent: 3742460 (1973-06-01), Englund
patent: 3772658 (1973-11-01), Sarlo
patent: 3895360 (1975-07-01), Cricchi
patent: 3913075 (1975-10-01), Vitaliev

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