Content addressable memory match line sensing techniques

Details Content addressable memory match line sensing techniques Content addressable memory match line sensing techniques

2003-03-14

2004-10-26

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S207000

Reexamination Certificate

active

06809945

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to memory cells and more particularly relates to content addressable memory cells.
Many memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory access. The time required to find an item stored in memory can be reduced considerably if the stored data item can be identified for access by the content of the data itself rather than by its address. Memory that is accessed in this way is called content-addressable memory (CAM). CAM provides a performance advantage over other memory search algorithms (such as binary and tree-based searches or look-aside tag buffers) by comparing the desired information against the stored data simultaneously, often resulting in an order-of-magnitude reduction of search time.
A CAM typically has two sets of sense amplifiers, amplifiers for read data sensing and for match line signal sensing. Referring to
FIG. 1
, a CAM
10
includes a row
20
of CAM cells, including CAM cells
22
-
24
.
Each of cells
22
-
24
is connected through bit lines, such as lines
38
-
39
, to a read sense circuit, such as circuit
26
. Circuit
26
comprises a differential amplifier that receives input from lines
38
-
39
.
Cells
22
-
24
are connected to a group
30
of corresponding match switches
32
-
34
that are connected to a match line
36
and connected to a source of reference potential
35
. Each of match switches
32
-
34
is switchable to a first state in the event of a match between data stored in a corresponding cell and test data introduced on bit lines and is switchable to a second state in the event of a mismatch between data in the corresponding cell and the test data on the bit lines.
Match line
36
is coupled to a match sense circuit
40
. Rather than using a differential amplifier as found in read sense circuit
26
, a conventional match sense circuit employs an asymmetric circuit, such as transistors
41
-
42
, which are not identical. Another transistor
43
is connected between transistors
41
-
42
and ground potential as shown. A supply voltage is used as a reference voltage applied to terminal
44
. In order to sense the voltage state of line
36
, the circuit senses the asymmetric ratio of the reference voltage and the voltage on line
36
. The differential sensed margin must remain relatively high for variations of power supply, temperature, wafer process variation, and the influences of skew lots. This requirement reduces the margin of accuracy for the circuit, reduces the speed at which the voltage state of line
36
can be sensed, and requires laborious and increased design time for each different technology used to implement the CAM. This invention addresses these problem and provides a solution.
U.S. Pat. No. 5,598,115 (Holst, issued Jan. 28, 1997) describes in
FIG. 17
a second match line
192
′ connected to transistors
196
′ and
197
. The circuit shown in Holst has disadvantages that are overcome by using the embodiments described in this application. For example, the ability of sense amplifier
190
to sense the differential voltage on lines
192
and
192
′ is dependent on the elapsed time period after precharge of those lines. After a sufficient time period, both lines
192
and
192
′ discharge to 0 volts, thereby preventing sense amplifier
190
from sensing a differential voltage. More specifically, transistor
197
may discharge the second match line
192
′ to 0 volts even if one or more of transistors
196
discharge line
192
, thereby preventing sense amplifier
190
from determining whether the voltages on lines
192
and
192
′ represent a match or a mismatch. A lengthening of the time period may occur during the process of testing the circuit shown in FIG.
17
. For example, if the circuit shown in
FIG. 17
is normally clocked a 100 MHz, it may be clocked during testing at a lower rate, such as 10 MHz. At the 10 MHz rate, both lines
192
and
192
′ may discharge to 0 volts, thereby preventing sense amplifier
190
from sensing a differential voltage. The same problem can occur if the
FIG. 17
circuit is clocked at various rates for different applications, or if the circuit is used with only a limited number of columns of CAM cells, such as less than 10. The embodiments described in this specification address the problems presented by the Hoist circuitry and provide a solution.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
One apparatus embodiment of the invention is useful in a content addressable memory comprising a group of content addressable cells and a group of corresponding match switches coupled by a first match line. Each match switch is switchable to a first state in the event of a match between data stored in a corresponding cell and test data and is switchable to a second state in the event of a mismatch between data in the corresponding cell and the test data. The first match line is switched to a first voltage in the event all of the match switches in the group are in the first state and is switched to a second range of voltages in the event one or more of the match switches in the group are in the second state. In such an environment, the state of the first match line is detected by apparatus comprising a second line and a second switch outside the group of corresponding match switches coupled to the second line. A third switch outside the group of corresponding match switches is coupled in series with the second switch. A differential amplifier is coupled to the first match line and the second line and is arranged to detect the difference in voltage between the first match line and the second line.
One method embodiment of the invention is useful in a content addressable memory comprising a group of content addressable cells and a group of corresponding match switches coupled by a first match line and coupled to a source of reference potential. Each match switch is switchable to a first state in the event of a match between data stored in a corresponding cell and test data and is switchable to a second state in the event of a mismatch between data in the corresponding cell and the test data. The first match line is switched to a first voltage in the event all of the match switches in the group are in the first state and is switched to a second range of voltages in the event one or more of the match switches in the group are in the second state. In such an environment, the state of the first match line is detected by a method comprising placing a second line in the environment of the first match line and limiting the voltage on the second line to a predetermined range of voltages relative to the reference potential. The difference in voltage between the first match line and the second line is detected.
By using the foregoing techniques, the state of a match line can be detected with a degree of accuracy and reliability previous unattained.
These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.


REFERENCES:
patent: 5483479 (1996-01-01), Osawa et al.
patent: 5598115 (1997-01-01), Holst
patent: 5642114 (1997-06-01), Komoto et al.
patent: 5905668 (1999-05-01), Takahashi et al.
patent: 6061262 (2000-05-01), Schultz et al.
patent: 6091655 (2000-07-01), Yamada et al.
patent: 6128207 (2000-10-01), Lien et al.
patent: 6147891 (2000-11-01), Nataraj
patent: 6191970 (2001-02-01), Pereira
patent: 6195277 (2001-02-01), Sywyk et al.
patent: 6307798 (2001-10-01), Ahmed et al.
patent: 6496395 (2002-12-01), Tokunaga et al.
patent: 6552920 (2003-04-01), Chadwick et al.
patent: 07 282586 (1995-10-01), None

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