Content addressable memory having a pair of memory cells storing

Details Content addressable memory having a pair of memory cells storing Content addressable memory having a pair of memory cells storing

1993-02-19

1996-10-22

Gossage, Glenn

Static information storage and retrieval

Associative memories

Ferroelectric cell

395435, 395419, 364DIG1, 365218, G11C 1504, G06F 1210

Patent

active

055684157

ABSTRACT:
A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors connects a common node to a respective one of a pair of address lines, and another of the transistors connects the common node to a potential of a predefined logic level. Each of the transistors has a gate receiving a logic level of the bit of information stored in a respective memory cell so that one of the transistors is conductive in response to the logic level of the bit of the information when the other of the transistors is not conductive in response to the logic level of the bit of information. Each of the memory cells also includes a transistor connected to the match line and having a gate connected to the common node. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care states permit multiple virtual page numbers to match a single entry storing information for multiple physical pages. The invalid state eliminates the need for a dedicated valid bit in each entry.

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