Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2000-12-05
2002-01-15
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S185080, C365S189070
Reexamination Certificate
active
06339540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile content-addressable memory (NVCAM) array implemented using a virtual-ground flash memory architecture.
2. Description of Related Art
Content-addressable memory (CAM) arrays are used in various applications where a fast searching capability is needed. Non-volatile CAM (NVCAM) arrays form a sub-class within this family. One example of a NVCAM array is described in U.S. Pat. No. 5,808,929.
While it is relatively easy to implement a CAM structure for a conventional non-volatile memory array that implements a common-source configuration, the task becomes more complex for a non-volatile memory array that implements a virtual-ground configuration. For example, U.S. Pat. No. 5,917,743 requires eight transistors to form a CAM cell and, in addition, requires the fabrication of a special isolation device.
It would therefore be desirable to have a NVCAM structure having a virtual-ground configuration that overcomes the deficiencies of the prior art.
SUMMARY
An object of the present invention is to provide a dense NVCAM array that utilizes a virtual-ground architecture. A first embodiment of the present invention can utilize either 1-bit or 2-bit non-volatile memory transistors, and achieves three transistor/bit density with no speed compromise. A second embodiment of the present invention can utilize either 1-bit or 2-bit non-volatile memory transistors, and achieves 2 transistor/bit density, with a two times degradation is speed. Third and fourth embodiments of the present invention utilize 2-bit non-volatile memory transistors and yield 1.5 and 1 transistor/bit density, with two-times and three-times degradation in speed, respectively. A fifth embodiment utilizes 2-bit non-volatile memory transistors and yields three separate three transistor/bit density arrays.
The first embodiment includes a content addressable memory (CAM) array having an array of 1-bit or 2-bit non-volatile memory transistors arranged in a plurality of rows and columns. Each memory transistor has a gate, a first device terminal and a second device terminal. A plurality of horizontally aligned compare lines are configured to receive a comparand word, wherein each compare line is coupled to the gate of each memory transistor in a row of the array. Vertically aligned device terminals in the array are coupled to form a plurality of word lines.
Selected columns of memory transistors are configured to store words in the array. One column of memory transistors adjacent to each selected column of memory transistors is unused (blank). In the first embodiment, two memory transistors are used to represent each bit of information. Thus, one memory transistor stores the data bit, while a corresponding memory transistor stores the complement of the data bit.
Consequently, three columns of memory transistors are effectively used to store two columns of data, thereby making the overall efficiency of the NVCAM array equal to three transistors/bit.
A compare operation is performed as follows. The compare data values are applied to the compare lines. Two compare lines are used for each bit, with one compare line receiving the compare data bit, and the other compare line receiving the complement of the compare data bit. Each column of memory transistors has two associated word lines. One of these word lines is coupled to receive a voltage of about 0 Volts (virtual ground). The other one of these word lines is coupled to receive a read reference voltage (e.g., 2 Volts) through a current sensing amplifier. If no current flows through the sense amplifier, then a match exists for the associated word. No current will flow through the sense amplifier if and only if, for all of the transistors in the column, either the compare line is at a low state or the transistor is programmed (i.e., does not conduct).
The second embodiment is similar to the first embodiment; however, in the second embodiment, all of the columns of the NVCAM array are used to store data values. In the second embodiment, a comparison operation is divided into two consecutive compare phases. In the first compare phase, a first set of words (columns) is compared with the comparand word. During the second compare phase, a second set of words (columns) is compared with the comparand word. The first and second compare phases are implemented by changing the functionality of the sense amplifiers during the two compare phases. In the second embodiment, the overall efficiency of the NVCAM array is equal to two transistors/bit, with the comparison operation taking twice as long as the comparison operation of the first embodiment.
The third embodiment includes an array of 2-bit non-volatile memory transistors arranged in a plurality of rows and columns, wherein selected columns of memory transistors are configured to store words. Again, each column of memory transistors that is selected to store a word is bordered by one unused column of memory transistors. In the selected columns, the two bits of each memory transistor are used to store a bit and a complementary bit of a corresponding word.
A comparison operation in the third embodiment is performed over two phases. A plurality of compare lines are provided, wherein each of the compare lines is coupled to the gates of the memory transistors in a corresponding row of the array. The compare lines are coupled to receive a comparand word during the first compare phase and a complement of the comparand word during the second compare phase.
Switches are provided to enable the word lines/sense amplifiers to be biased in a first direction during the first compare phase, thereby accessing a first bit of the 2-bit memory transistors. These switches are controlled to bias the word lines/sense amplifiers in a second direction during the second compare phase, thereby accessing a second bit of the 2-bit memory transistors. Sequential logic elements can be coupled to the output terminals of the sense amplifiers to store the results of the first and second compare phases.
The fourth embodiment includes an array of 2-bit non-volatile memory transistors arranged in a plurality of rows and columns, wherein each column of memory transistors is configured to store two words. Within each column, two memory transistors are used to represent each bit of information for each of the two words. Thus, one memory transistor stores two data bits, while a corresponding memory transistor stores the complement of those two data bits. A plurality of compare lines are provided, wherein each of the compare lines is coupled to the gates of the memory transistors in a corresponding row of the array.
In the fourth embodiment, a compare operation is performed over three compare phases. The compare lines are coupled to receive a comparand word and the complement of the comparand word during each of the three compare phases.
Switches and sense amplifiers are provided to enable the word lines to be biased in a first manner during a first compare phase, in a second manner during a second compare phase, and in a third manner during a third compare phase. Sequential logic elements can be coupled to the sense amplifiers to store the results of the first, second and third compare phases.
The fifth embodiment is similar to the fourth embodiment. However, in the fifth embodiment, the results of the first, second and third compare phases are considered separately, thereby effectively providing for three separate NVCAM arrays within a larger array. Each compare operation in the fifth embodiment is performed during a single compare phase.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5808929 (1998-09-01), Sheikholeslami et al.
patent: 5917743 (1999-06-01), Roy
patent: 6166938 (2000-12-01), Wong
patent: 6256216 (2001-07-01), Lien et al.
Ho Hoai V.
Hoffman E. Eric
Law Offices of Bever, Hoffman & Harms, LLP
Tower Semiconductor Ltd.
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