Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2002-02-05
2004-03-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S154000, C365S214000, C365S189050, C365S189080, C365S230030, C365S230040, C365S230050, C365S230060, C365S230080, C365S233100
Reexamination Certificate
active
06707692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a content addressable memory (CAM) device which can be used as a binary CAM device, and also as a ternary CAM device in which ternary data, including binary data and “X (don't care),” can be specified, and to structure methods therefor.
2. Description of the Related Art
As Internet technologies have advanced in these years, it has been demanded that network relay apparatuses, such as switching hubs and routers, operate at high speeds with high-level functions. To satisfy such a demand, these relay apparatuses have used CAM devices for processing, such as address filtering and packet classification, in many cases.
CAM devices have also been used in layers
2
,
3
, and
4
of the network Open Systems Interconnection (OSI) model in many cases. In these cases, the length of search key data varies from 32 bits to more than 256 bits; conventionally binary CAM devices, which can have only “0” and “1” as data, are sufficient in some cases; and ternary CAM devices, which can have “0,” “1,” and “X (don't care)” as data, are required in other cases.
Conventional binary CAM and ternary CAM devices will be described below.
FIG. 10
is a structural block diagram of a conventional CAM device.
The CAM device
90
shown in
FIG. 10
is provided with a m-bit by n-word CAM array
92
; an input-and-output (I/O) circuit
94
for driving write-in data, read-out data, and search data; a decoder
96
for decoding an address signal ADR to specify a CAM word corresponding thereto; and a priority encoder
98
for encoding the match lines word for which matching has been detected, according to a priority and for outputting the addresses of the CAM words having the match lines.
In the CAM device
90
, write-in data input from the outside by the I/O circuit
94
is written into a CAM word selected by the decoder
96
according to an address signal ADR, as storage data. Storage data is read from a CAM word selected by the decoder
96
and output to the outside by the I/O circuit
94
as read-out data.
Search data input from the outside is driven by the I/O circuit
94
, and a search operation is performed between the search data and storage data for all CAM words. The result of search for each CAM word is input to the priority encoder
98
through a match line, and the memory address of a CAM word for which matching has been detected is sequentially output as a highest hit address (HHA), according to a predetermined priority.
A binary CAM device has binary CAM cells, and a ternary CAM device has ternary CAM cells.
FIG. 11
is a circuit diagram of a binary CAM cell used in a conventional CAM device. The binary CAM cell
100
shown in
FIG. 11
is formed of a data storage portion
102
for storing one-bit data, “0” or “1,” and a match detector
104
for comparing data stored in the data storage portion
102
with search data input from the outside of the CAM device and for outputting a matching-detection result.
The data storage portion
102
is formed of a static RAM (SRAM) conventionally known to the public, and includes two inverters
46
a
and
46
b
and two n-type MOS transistors (NMOSS)
48
a
and
48
b
. In the two inverters
46
a
and
46
b
, the output terminal, of each of them is connected to the input terminal of the other. The NMOS
48
a
is connected between the input terminal of the inverter
46
a
and a bit line BL, and the NMOS
48
b
is connected between the input terminal of the inverter
46
b
and a bit bar line /BL. The gates of the two NMOSs are connected in common to a word line WL.
The match detector
104
is formed of four NMOSs
50
a
,
50
b
,
52
a
, and
52
b
. The NMOSs
50
a
and
52
a
are connected in series between a match line ML and the ground, the gate of the NMOS
50
a
is connected to the output terminal (D) of the inverter
46
b
, and the gate of the NMOS
52
a
is connected to the bit line BL. The NMOSs
50
b
and
52
b
are connected in series between the match line ML and the ground, the gate of the NMOS
50
b
is connected to the output terminal (/D) of the inverter
46
a
, and the gate of the NMOS
52
b
is connected to the bit bar line /BL.
In the binary CAM device having the binary CAM cell
100
, searching is performed in a way in which the bit line BL and the bit bar line /BL are set to a low level to turn off the NMOSs
52
a
and
52
b
, the match line ML is pre-charged to a power potential, and then, search data is driven to the bit bar line /BL and search data bar is driven to the bit line BL.
When storage data matches the search data, since the NMOS
52
a
or
52
b
connected in series to whichever is on according to the storage data, of the NMOSs
50
a
and
50
b
becomes off, the match line ML maintains a pre-charge state. On the other hand, if no matching is found, since the NMOS
52
a
or
52
b
corresponding to whichever is on, of the NMOSs
50
a
and
50
b
becomes on, the match line ML is discharged through whichever pair is both on, of the NMOSs
50
a
and
52
a
, and the NMOSs
50
b
and
52
b.
FIG. 12
is a structural circuit diagram of a ternary CAM cell used in a conventional CAM. The ternary CAM cell
106
is formed of a data storage portion
102
having the same structure as in the above-described binary CAM cell
100
, a mask-data storage portion
108
for storing data which determines whether to mask matching detection between storage data stored in the data storage portion
102
and search data, and a match detector
110
for comparing the storage data stored in the data storage portion
102
with the search data when masking is not performed by the mask-data storage portion
108
and for outputting a matching-detection result.
The mask-data storage portion
108
is formed of a static RAM (SRAM) in the same way as for the data storage section
102
, and includes two inverters
112
a
and
112
b
and two NMOSs
114
a
and
114
b.
The match detector
110
has a NMOS
116
in addition to the components of the match detector
104
of the binary CAM cell
100
shown in FIG.
11
. The NMOS
116
is connected between a match line ML and the drains of the NMOSs
50
a
and
50
b
, and its gate is connected to the output terminal (/M) of the inverter
112
a
of the mask-data storage portion
108
.
A search operation in the ternary CAM device having the ternary CAM cell
106
is performed in a way in which, when the mask-data storage portion
108
stores “0” as mask data M (M=0, /M=1), since the NMOS
116
in the match detector
110
is turned on, the ternary CAM device performs the same function as the binary CAM device having the above-described binary CAM cell
100
. On the other hand, when the mask-data storage portion
108
stores “1” as mask data M (M=1, /M =0), since the NMOS
116
is turned off, the match line ML has a high level irrespective of the state of the storage data (D), namely, always maintains a match state.
In this way, the CAM device having the ternary CAM cell
106
allows the search function to be masked by independently specifying a “don't care” for the CAM cell of each bit constituting each word. This function is called a local mask. In contrast, there has been known to the public a CAM device having a function for masking a search function for the same-position bits of all CAM words by applying “0” to the bit line BL and the bit bar line /BL. This function is called a global mask.
Conventional binary CAM devices having the above structure cannot be used as ternary CAM devices because a “don't care” cannot be specified as storage data itself in the binary CAM devices.
When conventional ternary CAM devices are used as binary CAM devices, all mask data used for specifying a “don't care” needs to be set to a no-mask state. In this case, however, since mask bits unnecessary for binary CAM devices are provided, an increase in bit cost occurs. In addition, a data writing operation needs to be performed twice, once for the data storage portion and once for the mask-data storage portion, in the
Kawasaki Microelectronics Inc.
Nelms David
Oliff & Berridg,e PLC
Pham Ly Duy
LandOfFree
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