Content addressable memory device

Details Content addressable memory device Content addressable memory device

1989-10-20

1991-09-24

Popek, Joseph A.

Static information storage and retrieval

Associative memories

Ferroelectric cell

365185, 365182, G11C 1500

Patent

active

050519484

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device, and more particularly, it relates to improvement in a content addressable memory (CAM) device.


BACKGROUND OF THE INVENTION

FIG. 35 is a circuit diagram showing a CAM cell which is disclosed in IEEE Journal of Solid State Circuits vol. sc-7, No. 5, Oct. 1972, pp. 364-369. A first conducting terminal of a first insulated gate field effect transistor M.sub.W1 (supposed to be an n-MOS transistor in this case) is connected to a first bit line BL, and its control terminal (gate) is connected to a word line WL. Similarly, a first conducting terminal of a second n-MOS transistor M.sub.W2 is connected to a second bit line BL, and its gate is connected to the word line WL.
A first conducting terminal of a third n-MOS transistor M.sub.S1 is connected to the first bit line BL, and its gate is connected to a second conducting terminal of the first transistor M.sub.W1. Similarly, a first conducting terminal of a fourth n-MOS transistor M.sub.S2 is connected to the second bit line BL, and its gate is connected to a second conducting terminal of the second transistor M.sub.W2.
A first conducting terminal of a fifth n-MOS transistor M.sub.D is commonly connected to respective second conducting terminals of the third and fourth transistors M.sub.S1 and M.sub.S2, while its gate and second conducting terminal are commonly connected to a match line ML.
In the conventional CAM cell structured in the aforementioned manner, the first bit line BL is brought into an "H" level and the second bit line BL is brought into an "L" level since the memory cell is formed by the n-MOS transistors. The first transistor M.sub.W1 is turned on if the word line WL enters an "H" level at this time, and hence positive electric charges are stored in the gate of the third transistor M.sub.S1 from the first bit line BL which is at the "H" level, whereby the third transistor M.sub.S1 is also turned on. On the other hand, the second transistor M.sub.W2 is also turned on in response to the "H" level of the word line WL, while the fourth transistor M.sub.S2 enters an off state since the gate of the fourth transistor M.sub.S2 is connected to the second bit line BL which is at the "L" level. Writing of information (data) is completed when the word line WL is brought into an "L" level in this state. It is assumed here that this storage state is data logic "1".
In order to retrieve stored data, the match line ML is precharged at an "H" level, and data to be referred to is supplied to the bit line pair BL and BL. Supposing that "1" is supplied as reference data, the first bit line BL is brought into an "H" level and the second bit line BL is brought into an "L" level. At this time, the fifth transistor M.sub.D is turned on since the match line ML is at the "H" level, while the match line ML is connected with the first bit line BL and cut off from the second bit line BL since the third and fourth transistors M.sub.S1 and M.sub.S2 are in on and off states respectively in the aforementioned storage state "1". However, the "H" level of the match line ML is maintained since the first bit line BL is at the "H" level. Namely, it can be recognized that the stored data matches the reference data since the precharge level "H" of the match line ML is maintained.
When "0" is supplied as the reference data, on the other hand, the first bit line BL is brought into an "L" level and the second bit line BL is brought into an "H" level. At this time, charges are extracted from the match line ML being at the "H" level to the first bit line BL being at the "L" level through the fifth transistor M.sub.D and the third transistor M.sub.S1 which are in on states, whereby the match line ML, which is in a floating state, enters an "L" level. Namely, it can be recognized that the stored data mismatches the reference data since the precharge level "H" of the match line ML is changed to "L".
FIG. 36 is a circuit diagram showing a CAM cell which is disclosed in Japanese Patent Laying-Open G

REFERENCES:
patent: 4408303 (1983-10-01), Guterman et al.
patent: 4538243 (1985-08-01), Zetiner
patent: 4831585 (1989-05-01), Wade et al.
patent: 4833643 (1989-05-01), Hori
Mundy et al., "Low-Cost Associative Memory," IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 364-369.
Grise et al., "Non-Volatile, Static-Access Memory Cell," IBM Technical Disclosure Bulletin, vol. 26, No. 1, Jun. 1983, p. 191.

Affiliated with

Also associated with

Rating

Content addressable memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Content addressable memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Content addressable memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1702609