Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2000-10-25
2001-10-09
Mai, Son (Department: 2811)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189070
Reexamination Certificate
active
06301140
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronic circuits. More particularly, this invention relates to integrated electronic circuits having content addressable memory, CAM.
BACKGROUND OF THE INVENTION
Content addressable memories, CAMs, are used in a variety of applications, such as sorting large databases, image recognition, and to index addresses on microprocessor chips. In a CAM, a multi-bit boolean data word is broadcast to an associative array. The associative array compares the incoming data word to each of the data words stored in the rows of the array. When the bits of the input match the bits of a word stored in any row of the associative array, it is called a match. When a match occurs, a signal is generated that is used to address a secondary array.
A CAM may be used in a microprocessor to create a look-up table that relates local or cache memory data to some hierarchical location in a microprocessor's main memory. In a simple form, if data has been transferred from main memory to a local cache memory, then the central processing unit, CPU needs to know that the data is stored locally. To make this determination, at least part of the address of the data from main memory is compared in the content addressable memory. If there is a match, or “hit”, that data, plus the address that is generated from the CAM's secondary array, is used to inform the CPU where to find the data.
Integrated circuits such as dynamic random access memory, DRAMs, static random access memory, SRAMs, and microprocessors may include thousands of electronic circuits which may result in millions of transitions being placed on a chip. The cost of an individual chip can be reduced if the circuits comprising the chip are educed in size. Therefore, it is desirable to reduce the size of the circuits included on any VLSI chip. The physical size of a microprocessor may be dominated by the memory portion of the chip. Thus, it is desirable that the individual cells that make up a memory circuit be as small as possible.
SUMMARY OF THE INVENTION
In a preferred embodiment, the invention provides a content addressable memory cell using bootstrapping techniques to increase voltage on gates of transfer n-channel field effect transistors, (NFETs) connected bet nodes. A CAM cell embodying the invention, may be applied to reduce the physical size of an integrated circuit, reduce the read access time of the CAM, reduce the write access time of a CAM, and reduce the compare access time of a CAM. The invention may be easily adapted to many technologies used to fabricate integrated circuits.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 4833643 (1989-05-01), Hori
patent: 5111427 (1992-05-01), Kobayashi et al.
patent: 5453948 (1995-09-01), Yoneda
patent: 6181591 (2001-01-01), Miyatake et al.
Hill J. Michael
Lachman Jonathan E.
Mellinger Todd W.
Hewlett--Packard Company
Mai Son
Pessetto John
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