Content addressable memory cell techniques

Details Content addressable memory cell techniques Content addressable memory cell techniques

2005-06-07

2005-06-07

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S154000, C365S189070

Reexamination Certificate

active

06903952

ABSTRACT:
A content addressable memory cell (10) includes a circuit (20) operating from a predetermined supply voltage (VDD) for storing a first bit of data at a first point (35) and a second bit of complementary data at a second point (36). A first transistor (40) comprising a first gate (42) is switchable to first and second states in response to predetermined relationships between the first and second bits and third and fourth test bits transmitted on first and second lines (14and16). Second and third transistors (50, 60) comprise gates (52, 62) coupled to the first line (14) and second line (16) and comprise circuit paths (54, 56, 64, 66) coupling the first and second points to the first gate.

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Ghosh et al., “Novel Content Addressable Memory,”Electronics Letters, IEE Stevenage, GB, vol. 25, No. 8, Apr. 13, 1989, pp. 524-526.

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