Content addressable memory cell providing simultaneous read...

Details Content addressable memory cell providing simultaneous read... Content addressable memory cell providing simultaneous read...

1999-09-09

2001-03-27

Phan, Trong (Department: 2878)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S180000

Reexamination Certificate

active

06208544

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to digital data storage circuitry, and is particularly directed to a new and improved content addressable, or associative, memory cell architecture, that is configured to allow simultaneous read and compare operations.
BACKGROUND OF THE INVENTION
Because digital signal processing circuit designers continue to use the same hardware building blocks, such as the (static) random access memory (RAM), MOSFET-configured, data bit cell diagrammatically illustrated in
FIG. 1
, to implement a variety of product designs, enhancements in system performance have been essentially governed by improvements in line widths and manufacturing processes of integrated circuit components that enable data processing architectures to operate at faster speeds and store more data in smaller volumes of semiconductor material.
Although the memory cell of
FIG. 1
is shown as a metal oxide semiconductor (MOS) transistor-configured cell, it should be observed that the cell may be implemented using other components, such as but not limited to bipolar devices, biCMOS devices, and the like. In the example shown in
FIG. 1
, the MOSFET memory cell, shown at
10
, is comprised of a pair of cross-connected inverters
11
and
12
that are coupled to power supply rails V
DD
, V
GG
and ground (GND), and having complementary data bit nodes D and D BAR that store complementary bit logic levels representative of the data bit stored in the cell. MOS transistors T
1
and T
2
are the respective drive and load transistors of inverter
11
, while MOS transistors T
3
and T
4
are the respective drive and load transistors of the other inverter
12
. Within a memory comprised of two-dimensional array of such cells, the X and Y locations, and therefore the address, of the memory cell are defined by an X node
21
, that is coupled to the X address node of other memory cells of the same row of the memory array, and a Y node
22
, that is coupled to the Y address node of other memory cells of the same column of the memory array.
The X node
21
is coupled to the gates of row address transistors T
5
and T
6
, which have their source-drain paths coupled between respective data nodes D and D BAR and complementary Data and Data BAR lines
31
and
32
. The Data and Data BAR lines
31
and
32
are coupled to other memory cells of the same Y column of the memory array. The Y node
22
is coupled the gates of column address transistors T
7
and T
8
, which have their source-drain paths respectively coupled in circuit with the source-drain path of a data input (or write) transistor T
9
and a data output (or read) transistor T
10
.
To store or write data into the memory cell, the source-drain path of data input transistor T
9
is coupled to a data input (Data in) node
41
and its gate is coupled to receive a write control signal W. To read data from the memory cell, the source-drain path of data output transistor T
10
is coupled to a data output (Data Bar out) node
42
and its gate is coupled to receive a read control signal R. When writing or reading data, the cell is addressed by applying a prescribed logic level (e.g., ‘1’) to the respective X and Y,address nodes
21
and
22
, so as to turn on transistors T
5
, T
6
, T
7
and T
8
. With transistors T
5
and T
7
turned on, the data node D is coupled to data input transistor T
9
, while the complementary data node D BAR is coupled to the data output transistor T
10
.
In order to write data into the memory cell
10
, the write control input W to the gate of data input transistor T
9
is asserted at a prescribed logical state (e.g., ‘1’), while the read control input R to the gate of data output transistor T
10
is asserted at a complementary logical state (e.g., ‘0’), thereby turning on transistor T
9
and holding transistor T
10
off during a respective ‘write cycle’. If the bit value applied to the Data in node
41
is a ‘1’, the resulting ‘1’ at data node D turns on transistor T
3
, thereby coupling the complementary data node D BAR to GND or ‘0’. Namely, the data line
31
is at the input data value ‘1’, while the complementary data line D BAR
32
is at a logical ‘0’ value. On the other hand, if the bit value applied to the Data in node
41
is a ‘0’, the resulting ‘01’ at data node D turns transistor T
3
off, so that complementary data node D BAR is at a logical ‘1’. In this case, the data line
31
is at the input data value ‘0’, while the complementary data line D BAR
32
is at a logical ‘1’ value.
To read data from the memory cell
10
, the read control input R to the gate of data input transistor T
10
is asserted at a prescribed logical state (e.g., ‘1’), while the write control input W to the gate of data input transistor T
9
is asserted at a prescribed complementary logical state (e.g., ‘0’), thereby turning on transistor T
10
and holding transistor T
9
off. Since each of transistors T
5
, T
6
, T
7
and T
8
is turned on, then during this ‘read cycle’, whatever bit value is stored in the memory cell
10
will be coupled to Data line
31
, while its complement will be coupled to Data BAR line
32
.
In addition to being selectively addressable so as to allow data to be written into or read out, the memory cell may be configured as an associative or content addressable memory (CAM) cell, that enables its stored data bit to be compared or associated with a prescribed ‘comparison’ bit value. For this purpose, the memory cell of
FIG. 1
may be augmented as diagrammatically illustrated in
FIG. 2
to include a bit value comparator or ‘match’ circuit
50
, that is coupled to the data nodes and data lines of the cell.
A typical comparator employed for this purpose may comprise an exclusive NOR circuit having first and second pairs of sense transistors T
11
-T
13
and T
12
-T
14
, with their drain-source paths coupled in circuit between a reference potential node (e.g., GND) and a compare or ‘MATCH’ line
51
, that is wire-AND coupled to other cells of the same word's key field. The gate of transistor T
11
is coupled to the data line side of the source-drain path of transistor T
5
, while the ‘sense’ input or gate of transistor T
13
is coupled to the data node D of the memory cell
10
. On the complementary side, the gate of transistor T
12
is coupled to the Data line BAR side of the source-drain path of transistor T
6
, while the ‘sense’ gate of transistor T
14
is coupled to the data node D BAR of memory cell
10
.
This auxiliary comparator circuitry allows the content addressable memory cell configuration of
FIG. 2
to conduct an associative or comparison operation during a match cycle that is separate from the write and read cycles in the manner described above with reference to FIG.
1
. In particular, during a comparison cycle, the match line
51
is charged to a prescribed (high) level. Since the purpose of an associative operation is to ‘assert data’ and ‘read address information’ , the X address node
21
is asserted low, so as keep transistors T
5
and T
6
turned off, thereby isolating the memory cell and preventing its contents from being affected by the comparison operation being performed. Also, the write W and read R control inputs are controllably multiplexed, so as to couple comparison data to the data lines through the input transistor T
9
and the data output transistor T
10
.
Namely, the data bit and its complement with which the bit stored in the memory cell is to be compared are selectively applied to the Data BAR line
32
and its complement Data line
31
, by turning on the transistors T
9
and T
10
, the source-drain paths of which are coupled to the gates of transistors T
12
and T
11
. Since the ‘sense’ gate of transistor T
13
is coupled to the data node D and the ‘sense’ gate of transistor T
14
is coupled to the data node D BAR of the memory cell
10
, a ‘match’ can occur only if the stored bit and the comparison bit have the same value.
Because both the write or data input transistor T
9
and the read or data output transistor T
10
are employed during a compariso

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