Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2003-05-22
2004-10-19
Tran, M. (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S129000
Reexamination Certificate
active
06807077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a content addressable memory (CAM) for determining whether search data is stored in accordance with the search data. More particularly, the present invention relates to a ternary content addressable memory (TCAM) capable of performing high-speed operation and stably storing ternary data.
2. Description of the Background Art
A content addressable memory (CAM) has functions of writing and reading data and, in addition, capable of addressing stored data in accordance with search data. Specifically, a CAM can detect whether stored data (word) which matches external data (search data), exists. When data matching the search data is stored, a match line is driven and it can be detected that data matching the search data is stored. Therefore, it is unnecessary to compare stored data with search data one by one, so that data search can be performed at high speed.
Such a CAM is used for, for example, address comparison at the time of determination of cache hit/miss for determining whether necessary data is stored or not in accessing a cache in a data processing system.
In a conventional CAM, a memory cell has, as storage states, two states of “1” and “0” and stores binary data. In the case of the CAM for storing binary data, non-ambiguous and meaningful data is stored for each word. In a search operation, when bits of stored data (word) completely match bits of search data, a match line is set to a state indicative of match.
A TCAM (Ternary CAM) for storing ternary data in place of a CAM cell for storing binary data is disclosed in U.S. Pat. No. 6,320,777 B1.
In the TCAM, as storage states, in addition to the two states of “1” and “0”, a “don't care (X)” state is stored in a memory cell. In the case of constructing each storage word by a combination of ternary data bits, it is particularly effective in the case of performing a process on an IP (Internet Protocol) packet in a network system. For example, it is now assumed that a destination address of a packet is expressed by four bits, for simplicity. When the destination address of a packet is “1***” (where the head bit is “1” and each of the remaining address bits may be any value), a predetermined process is assumed to be performed on the packet. In addition, to retrieve the destination address when the packet arrives at the system and determine whether the destination address matches the address “1***” or not, the content addressable memory CAM or the ternary CAM is assumed to be used.
In this case, the data “1***” has to be stored in the CAM or TCAM before the packet arrives. When a normal CAM for storing binary data is used, eight states of “1000”, “1001”, “1010”, “1011”, “1100”, “1101”, “1110”, and “1111” have to be stored. Therefore, for retrieval of the destination address of the packet, eight words are consumed.
By contrast, since a state “X” can be stored in the TCAM, TCAM is only required to store one word of “1XXX”. When the number of bits of the destination address further increases, the difference in the number of words to be used further increases. Therefore, in the case of using the TCAM, various data can be stored with a reduced number of words. In practice, an IP packet includes, in addition to the destination address, various information such as an IP address of a transmission source, information indicative of communication quality, and version number of an IP protocol. It is therefore understood that the TCAM is very useful in the case of performing a search process on the information.
As described above, the TCAM is a content addressable memory capable of storing ternary information and is useful as an LSI used for packet search information in an information network system.
In the prior art document as described previously, a DRAM (Dynamic Random Access Memory) cells of two bits are used to store 1-bit data, thereby achieving storage of ternary data. Specifically, data of “HL”, “LH” and “LL” is stored in two separate storage nodes of the DRAM cells, and a comparing circuit detects whether the data matches search data supplied via a search data line or not.
As described above, in the prior art document, a DRAM cell is used as a memory element. As a capacitive element for storing data in the DRAM cell, a three-dimensional capacitor of a stacked structure is used. If such stacked capacitor is used in the DRAM cell, it is excepted that the area of a TCAM cell can be reduced and the chip area is accordingly reduced. It is also expected that a capacitor, which occupies a small area but has a large capacitance value, can be implemented and a soft error immunity can be improved.
In the case of using such a stacked capacitor for a TCAM, however, in order to make the operation stable, it is necessary to form a capacitor of as large a capacitance value as possible. Consequently, the structure of a capacitor portion is complicated and a memory cell structure becomes a complicated three-dimensional structure. Accordingly, the number of processes and the number of masks increase, and complicated patterning has to be made, so that it becomes difficult to decrease the chip cost. Consequently, even when the stacked capacitor of the three-dimensional structure is used to reduce the TCAM cell area to reduce the chip area accordingly, it is difficult to dramatically decrease the manufacturing cost.
As for electric characteristics, usually, a DRAM cell capacitor can have a large capacitance value. On the other hand, it takes long time to charge the capacitor and it causes such a problem that write cycle time is increased. In the TCAM, when it is necessary to write data to an array, the data has to be written while interrupting a normal search operation. Therefore, in the case in which the write time is long, the interruption time against the search operation is correspondingly increased, and it causes such a problem that the search process efficiency deteriorates.
In the case of using the capacitor of a DRAM cell for storing data, in order to prevent stored data from being lost by leakage of charges, a refresh operation for restoring data has to be performed periodically. In performing the refresh operation, memory cell information is internally read, amplified and rewritten. Therefore, the refresh operation has to be performed also while interrupting the search operation. Since the interruption by the refresh operation to the search operation occurs in a major time portion, the search process efficiency deteriorates.
In the configuration of the TCAM cell shown in the prior art document 1, an open bit line structure for amplifying potentials of bit lines that are provided on the right and left sides of a sense amplifier is employed inevitably for the following reason. A sense amplifier is used to read and refresh data of the TCAM cell. A bit line is connected to a transistor in the DRAM cell in the TCAM cell and transmits write/read data.
The potentials of the storage nodes of the two capacitors in the TCAM cell are “H, L”, “L, H” or “L, L” in accordance with a storage state. Therefore, complementary voltages are not always stored in the two storage nodes. When data stored in the two capacitors of TCAM cell are read to first and second bit lines, voltages of the first and second bit lines cannot be differentially amplified by a sense amplifier. Thus, a normal folded bit line structure used in a DRAM cannot be used.
In the case of the folded bit line configuration, complementary data are always transmitted to a pair of bit lines, and a sense amplifier amplifies the difference of the potentials on the bit line pair. The bit line pair is disposed in parallel on one side of the sense amplifier. Even if noise occurs, common phase noises also occur on the bit line pair. Different from the open bit line configuration, the folded bit line configuration has an advantage that influences of noise are cancelled out and a very small potential difference can be stably amplified. In the case of the TCAM cell
Noda Hideyuki
Shimano Hiroki
McDermott Will & Emery LLP
Renesas Technology Corp.
Tran M.
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