Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2003-04-23
2004-02-24
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S189110, C365S203000
Reexamination Certificate
active
06697277
ABSTRACT:
BACKGROUND
The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for automatically adjusting the pull-up margin of a match line circuit used in conjunction with a content addressable memory (CAM).
A content addressable memory (CAM) is a storage device in which storage locations are identified by their contents, not by names or positions. A search argument is presented to the CAM and the location that matches the argument asserts a corresponding match line. One use for such a memory is in dynamically translating logical addresses to physical addresses in a virtual memory system. In this case, the logical address is the search argument and the physical address is produced as a result of the dynamic match line selecting the physical address from a storage location in a random access memory (RAM). CAMs are also frequently used for Internet address searching.
A conventional CAM array
1
having n-bit words is shown in
FIG. 1
to include a row of n CAM cells
10
coupled to an associated word line WL. Each CAM cell
10
includes a latch, formed by CMOS inverters
12
and
14
, for storing a bit of data. Opposite sides of the latch are coupled to associated complementary bit lines BL and BL bar via pass transistors
16
and
18
, respectively, where each transistor has a gate coupled to the associated word line WL. The output terminal of the inverter I
2
is coupled to the gate of an NMOS pass transistor
20
, and the output terminal of the inverter I
4
is coupled to the gate of an NMOS transistor
22
. Transistor
20
is coupled between the associated bit line BL and the gate of an NMOS pull-down transistor
24
, and transistor
22
is coupled between the associated complementary bit line BL bar and the gate of pull-down transistor
24
. Pull-down transistor
24
is coupled between ground potential and a match line ML associated with the CAM word formed by the cells
10
. A PMOS pull-up transistor
26
is coupled between a supply voltage V
DD
and the match line ML.
In the configuration of
FIG. 1
, the pull-up transistor
26
has a gate tied to ground potential and, therefore, remains in a conductive state. A conventional buffer
28
is coupled in series between the match line and an associated sensing circuit (not shown). During compare operations, the word line WL associated with the CAM word is grounded to turn off the pass transistors
16
and
18
associated with each CAM cell
10
. Comparand bits to be compared with the data bits Q stored in the CAM cells
10
are provided to the associated bit lines BL, while the respective complements of the comparand bits are provided to the associated complementary bit lines BL bar. For each CAM cell
10
, if the comparand bit matches the data bit Q stored therein, the gate of the corresponding pull-down transistor
24
is driven with a logic low signal via transistors
20
or
22
, thereby maintaining the pull-down transistor
24
in a non-conductive state. If, on the other hand, the comparand bit does not match the data bit Q stored in the CAM cell
10
, the gate of the corresponding pull-down transistor
24
is driven with a logic high signal via transistors
20
or
22
, thereby turning on the pull-down transistor
24
. When conductive, the pull-down transistors
24
pull the match line toward ground potential.
Thus, if just one of the comparand bits do not match their corresponding data bits Q stored in the CAM cells
10
, the match line ML will be pulled to a logic low state (i.e., ground potential). Conversely, if all of the comparand bits match their corresponding data bits Q, the match line ML remains at the supply voltage V
DD
(i.e., a logic high state). In response to the voltage level on the match line ML, the buffer
28
provides to an associated sense circuit (not shown) an output signal indicative of whether all bits of the comparand word match all corresponding bits of the CAM word.
One disadvantage of the above described CAM configuration results from the fact that during a standby mode, DC current will flow through the match line circuit unless the bitline nodes (BL, BL bar) are precharged low. Otherwise, the path to ground potential results in significant power dissipation which, in turn, undesirably increases as the size and/or density of the CAM increases. On the other hand, the use of additional circuitry to precharge the bitline pairs also have negative impacts on device size and cost.
BRIEF SUMMARY
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for determining a desired operating impedance for a computer memory circuit, the computer memory circuit having a plurality of discrete, selectively adjustable impedance values associated therewith. In an exemplary embodiment of the invention, the method includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. One of the binary count values represents a first impedance value which causes the reference circuit to change from the first state to the second state, and the other binary count value represents a second impedance value which causes the reference circuit to change from the first state to the second state. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.
In a preferred embodiment, the lower of the stored pair of binary count values is adjusted by subtracting a predetermined, fixed value therefrom so as to create a buffered count. The buffered count is then used in applying the desired operating impedance to the operating circuit.
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patent: 5740097 (1998-04-01), Satoh
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Rotella Jason
Towler Fred J.
Wistort Reid A.
Cantor & Colburn LLP
Elms Richard
Hur J. H.
Walsh Robert A.
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