Content addressable memory (CAM) for data lookups in a data...

Static information storage and retrieval – Associative memories – Ferroelectric cell

Reexamination Certificate

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C365S189070

Reexamination Certificate

active

07061782

ABSTRACT:
Power consumption is reduced in a content addressable memory of a data processing system or a data processor. The content addressable memory includes at least a first single bit storage (101; 301), a word line (WL), at least one bit write line (BLWT, BLWC) and a hit/miss line (H/M), and at least a first single bit compare circuit (201; 320), the first single bit storage including at least a first output (A; A0) and the first single bit compare circuit including at least a first compare bit input (BLCT; CB0) and two field effect transistors (113, 114; 312, 313). In order to reduce the power consumption, the first output (A; A0) of the single bit storage (101; 301) is applied to the gate of only one, a first field effect transistor (114; 312) of the two field effect transistors (113, 114; 312, 313). For an additional reduction of the power consumption, two single bit storages (101, 301) are connected to a shared compare circuit (319). In case of a mismatch, only one out of four compare nodes (C0, C1, C2, C3) of the shared compare circuit is switched high, i.e. changes its potential.

REFERENCES:
patent: 5351208 (1994-09-01), Jiang
patent: 5453948 (1995-09-01), Yoneda
patent: 6195278 (2001-02-01), Calin et al.

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