Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2006-08-15
2006-08-15
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S049130, C365S230030, C365S230040, C711S108000
Reexamination Certificate
active
07092311
ABSTRACT:
Content addressable memory devices may include a priority encoder therein and a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of the priority encoder. A priority class detector is also provided for efficiently communicating match information that is generated during a search operation. The priority class detector passes match information from a selected priority class of rows in a selected one of the CAM arrays in the first tier to the priority encoder. This operation to pass match information is performed in response to detecting a match in the selected priority class when a search operation is performed. The priority class detector performs operations to locally encode match lines associated with a respective CAM array by priority class. These match lines are associated with a plurality of consecutive rows or consecutive pairs of rows that are arranged in a repeating priority class sequence comprising different priority classes. The priority class sequence may be an alternating priority class sequence, with each physically even row (or even pair of rows) in a CAM array being associated with one priority class and each physically odd row (or odd pair of rows) in a CAM array being associated within another priority class. Alternative priority class sequences may also be provided.
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Integrated Device Technology Inc.
Myers Bigel & Sibley Sajovec, PA
Tran Andrew Q.
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