Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2002-02-27
2003-12-02
Le, Thong (Department: 2818)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S225700
Reexamination Certificate
active
06657878
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices and, more particularly, to content addressable memory (CAM) devices and methods of operating same.
BACKGROUND OF THE INVENTION
In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a compare operation to identify one or more locations within the array that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the compare operation, the identified location(s) containing equivalent data is typically encoded to provide an address at which the equivalent data is located. If multiple locations are identified in response to the compare operation, then priority encoding operations may be performed to identify a best or highest priority match. Such priority encoding operations frequently utilize the physical locations of multiple matches within the CAM array to identify a highest priority match. Exemplary CAM cells and CAM memory devices are more fully described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and U.S. Pat. Nos. 6,101,116, 6,256,216 and 6,128,207 to Lien et al., assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
CAM cells are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}.
Operations to perform a conventional compare operation will now be described more fully with respect to FIG.
1
A. In particular,
FIG. 1A
illustrates a conventional ten transistor (10T) CAM cell
10
. The CAM cell
10
includes an SRAM data cell and a compare circuit. The SRAM data cell includes first and second access transistors N
1
and N
2
and first and second inverters that are electrically coupled in antiparallel. The true and complementary inputs of the SRAM data cell are electrically coupled to a true bit line BIT and a complementary bit line BITB, respectively. The true and complementary outputs of the SRAM data cell are illustrated as nodes Q and QB, respectively. The compare circuit includes transistors N
3
-N
6
, with the gate of transistor N
6
operating as a true data input of the compare circuit and the gate of transistor N
4
operating as a complementary data input of the compare circuit. As illustrated, the true data input of the compare circuit is electrically connected to the true data line DATA and the complementary data input of the compare circuit is electrically connected to the complementary data line DATAB. As illustrated by the dofted lines, the true bit line BIT and the complementary data line DATAB may be electrically connected together as a first bit line and the complementary bit line BITB and the true data line DATA may be electrically connected together as a second bit line. The first and second bit lines may be treated as a pair of differential bit/data lines that support rail-to-rail (e.g., Vdd-to-Vss) signals.
The compare circuit is also electrically connected to a pair of signal lines. This pair of signal lines includes a match line and a pseudo-ground line (PGND) or ground line (Vss). The pseudo-ground line PGND is frequently referred to as a “low” match line (LM). The operation of a CAM cell that is responsive to a match line and pseudo-ground line PGND is more fully described in U.S. Pat. No. 6,262,907 to Lien et al., entitled “Ternary CAM Cell,” assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference. The match line and pseudo-ground line PGND are precharged high prior to a compare operation and then the pseudo-ground line PGND is pulled low at a commencement of the compare operation. During the compare operation, the potential of the match line can be monitored to determine whether or not the CAM cell
10
is associated with a matching entry within a CAM array. For example, if the SRAM data cell within the CAM cell
10
is storing a logic 1 value (Q=1 and QB=0) and the illustrated pair of data lines is driven with a matching logic 1 value (i.e., DATA=1 and DATAB=0), then transistors N
3
and N
6
within the compare circuit will be turned on and transistors N
4
and N
5
within the compare circuit will remain off. Under these conditions, the series electrical connection provided by transistors N
3
and N
4
and the series electrical connection provided by transistors N
5
and N
6
will both remain nonconductive. Accordingly, the CAM cell
10
will not operate to electrically connect (i.e., “short”) the match line and pseudo-ground line PGND together and, therefore, will not operate to pull-down the match line from its precharged high level. In contrast, if the SRAM cell within the CAM cell
10
is storing a logic 0 value (Q=1 and QB=0) and the illustrated pair of data lines is driven with an logic 1 value (i.e., DATA=1 and DATAB=0), then transistors N
5
and N
6
within the compare circuit will be turned on and transistors N
3
and N
4
within the compare circuit will remain off. Under these conditions, the series electrical connection provided by transistors N
5
and N
6
will become conductive and the match line will be pulled-down from its precharged high level.
Referring now to
FIG. 2
, a conventional nine transistor (9T) CAM cell
12
is illustrated. This CAM cell
12
includes an SRAM data cell and a compare circuit. The compare circuit includes three transistors N
7
-N
9
. When the SRAM data cell is storing a logic 1 value (i.e., Q=1 and QB=0), and the pair of differential data lines are driven with a logic 1 value (i.e., DATA=1 and DATAB=0), transistors N
7
and N
8
will remain off and node N will remain low at its precharged low level. Under these conditions, transistor N
9
will remain nonconductive and the CAM cell
12
will not operate to pull the match line low from its precharged high level. In contrast, if the SRAM data cell is storing a logic 0 value (i.e., Q=0 and QB=1), and the pair of differential data lines a
Lien Chuen-Der
Wu Chau-Chin
Integrated Device Technology Inc.
Le Thong
Myers Bigel & Sibley & Sajovec
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