Content addressable memory (CAM) devices having CAM array...

Details Content addressable memory (CAM) devices having CAM array... Content addressable memory (CAM) devices having CAM array...

2003-07-18

2004-12-07

Lam, David (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189011, C711S108000

Reexamination Certificate

active

06829153

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices and, more particularly, to content addressable memory (CAM) devices and methods of operating same.
BACKGROUND OF THE INVENTION
In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the device and then performing a search operation to identify one or more entries within the CAM device that contain data equivalent to the applied data and thereby represent a “match” condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., CAM array block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM device to identify a highest priority matching entry. An exemplary CAM device that utilizes a priority encoder to identify a highest priority matching entry is disclosed in commonly assigned U.S. Pat. No. 6,370,613 to Diede et al., entitled “Content Addressable Memory with Longest Match Detect,” the disclosure of which is hereby incorporated herein by reference. The '613 patent also discloses the use of CAM sub-arrays to facilitate pipelined search operations. Additional CAM devices are described in U.S. Pat. Nos. 5,706,224, 5,852,569 and 5,964,857 to Srinivasan et al. and in U.S. Pat. Nos. 6,101,116, 6,256,216, 6,128,207 and 6,262,907 to Lien et al., the disclosures of which are hereby incorporated herein by reference.
CAM cells are frequently configured as binary CAM cells that store only data bits (as “1” or “0” logic values) or as ternary CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an “unmasked” data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a “don't care” (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array block having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array block are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {
1011
}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {
1011
}, {X
011
}, {
1
X
11
}, {
10
X
1
}, {
101
X}, {XX
11
}, {
1
XX
1
}, . . . , {
1
XXX}, {XXXX}.
FIG. 1
herein illustrates a conventional CAM device having a plurality of CAM array blocks therein arranged in a plurality of rows and columns. The CAM array blocks in the first, second, third and fourth rows are illustrated as CAM
00
-CAM
07
, CAM
10
-CAM
17
, CAM
20
-CAM
27
and CAM
30
-CAM
37
. A respective row priority encoder is also provided between each pair of CAM array blocks. Thus, as illustrated, the CAM device of
FIG. 1
includes sixteen (16) row priority encoders (shown as Row Priority Encoder
00
-Row Priority Encoder
33
). These row priorty encoders perform final encoding of all match information generated by a respective pair of CAM array blocks. A respective global word line decoder is also provided for each row of CAM array blocks. As will be understood by those skilled in the art, each global word line decoder provides word line signals to the CAM array blocks of a respective row during reading and writing operations. These word line signals may be provided on global word lines. An exemplary row priority encoder is disclosed in U.S. Pat. No. 6,307,767 to Fuh.
Conventional techniques to reduce power consumption within CAM devices are disclosed in U.S. Pat. Nos. 6,191,969 and 6,191,970 to Pereira. In particular, the '969 patent discloses a CAM array having CAM cells therein that include a discharge circuit connected between each cell and a fixed ground potential. Each of the discharge circuits include a control terminal coupled to receive a control signal indicative of the logical state of a match line segment in a respective row. These discharge circuits may be turned off to prevent discharge of respective match line segments during a search operation. U.S. Pat. No. 6,243,280 to Wong et al. also discloses a conventional technique to reduce power consumption by providing selective precharge of match line segments during a search operation. U.S. Pat. No. 5,517,441 to Dietz et al. discloses the use of inverters and pull-down transistors to pass match line signals from one match line segment to another match line segment during a search operation. U.S. Pat. Nos. 5,446,685 and 5,598,115 to Hoist also disclose the use of rail-to-rail (i.e., Vdd-to-Vss) pulsed ground signals during search operations.
Notwithstanding these conventional techniques to reduce match line power consumption in partitioned CAM array blocks, there continues to be a need for techniques to further reduce power consumption in high capacity CAM devices having large numbers of CAM array blocks therein.
SUMMARY OF THE INVENTION
Content addressable memory (CAM) devices according to embodiments of the present invention conserve match line and bit line power when CAM array blocks therein are searched. These CAM array blocks are searched in a pipelined segment-to-segment manner to increase search speed. The pipelined search operations may also be interleaved with write and read operations in an efficient manner that reduces the occurrence of pipeline bubbles.
A CAM array according to an embodiment of the present invention includes a first plurality of rows CAM cells that are partitioned into at least two segments. These segments may include a xR segment and a xS segment. In some preferred embodiments, the xS segment may be longer than the xR segment. A match line control circuit is also provided. The match line control circuit may be disposed as a column of circuitry that extends between the xR and xS segments of the CAM array. In some embodiments, the match line control circuit includes a plurality of latches that are configured to receive a first plurality of match line signals developed in the xR segment during a xR search operation. The control circuit may also include boolean logic, which is electrically coupled to outputs of the plurality of latches. This boolean logic may be configured to evaluate match conditions determined by the plurality of match line signals and conserve power by selectively blocking discharge of at least one precharged pseudo-ground line segment in the xS segment of the CAM array during a xS search operation when the match conditions indicate that no matching entries are present in the first plural

Affiliated with

Also associated with

Rating

Content addressable memory (CAM) devices having CAM array... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Content addressable memory (CAM) devices having CAM array..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Content addressable memory (CAM) devices having CAM array... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3277610