Content addressable memory architecture and circuits

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307362, 3072723, 330288, H03F 345, H03K 5153

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active

052705919

ABSTRACT:
A BICMOS sense amplifier for content addressable memory circuits which combines the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices. A combination of an RS latch at the output of a bipolar sense amplifier storing this output, and a clamping device at the base of the bipolar sensing amplifier shorting the base to ground, bring the bipolar device out of saturation after each sensing cycle to improve the switching speed. A biasing network is designed to bring the base of the bipolar sense amplifier up to a base-emitter turn-on voltage, while maintaining the output at a high level to improve voltage sensitivity and switching speed. Current mirrors are used in the biasing network to optimize performance over temperature and process variations.

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Rosseel, G. O., et al., "A Single-Ended BiCMOS Sense Circuit for Digital Circuits," IEEE International SOlio-State Circuits Conference, 2 pp., (1989).

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