Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2001-06-28
2003-01-21
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S227000, C365S189070, C365S230060, C365S239000
Reexamination Certificate
active
06510069
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a content addressable memory (CAM) apparatus and a method of operating the same, and more particularly, to a content addressable memory (CAM) apparatus and a method of operating the same that can reduce the operation power consumption and the fabrication cost.
2. Description of the Related Art
The content addressable memory is a kind of storage apparatus for comparing specific data with the data stored in a CAM array. The whole CAM array or block is able to perform a parallel comparison with comparand data. Therefore, the comparison speed is fast, and the efficiency is promising. After parallel comparison, if the data stored in the CAM matches, the CAM apparatus outputs a match flag signal. Conversely, if no matched data is found, the CAM apparatus stores the comparand data into one of the idle memories of the CAM array.
Conventionally, the comparison between the comparand data and the data stored in the CAM array, and the refresh process of the non-iterate data (that is, the data not located in the CAM array is stored in the empty memory) require many commands and clock cycles to complete.
FIG. 1
shows a conventional CAM array
100
that includes 4 rows (4 words) and 4 columns (4 bits) with 16 core cells, 110 in total. Each core cell
110
includes a data storage apparatus (not shown) and a pair of bit lines
100
a.
The pair of bit lines
100
a
is used to transmit different data of one single bit instead of transmitting two-bit data. That is, if one bit line
100
a
carries a high potential level (logic 1), the other bit line
100
a
carries a low potential level (logic 0).
In addition, to store the data of one single bit, each core cell further performs a single bit compare operation (logic exclusive NOR comparison (XNOR)). All the bit lines
100
a
are connected to the reference word storage and bit line driver
102
to transmit different data. When the reference word storage and bit line driver
102
receive the parallel input data D and transmit the data to the memory cell of the CAM array
100
, the compare operation is complete. The CAM array
100
includes an encoder
104
, which is coupled to all the matching sense lines (MSL) to receive all the match flag signals.
The detailed operation method of the CAM apparatus is described in FIG.
2
. Each row comprises N CAM cells. Each CAM cell is divided into two portions. One is the static random memory cell (SRAM) portion, and the other is the tag-compare portion such as the transistors
114
a
to
114
d.
Such portion has the function to perform XOR (exclusive OR) on the data input from the bit lines
100
a
and the data stored in the SRAM (such as BIT
0
and {overscore (BIT
0
)} as shown in FIG.
2
).
However, this conventional CAM apparatus has many drawbacks. For example, for the first row illustrated in
FIG. 2
, all the word lines (WL
0
, WL
1
, . . . , WL
N
) corresponding to N CAM cells have to be turned on if a comparison operation is performed on the bit data of the input bit line
100
a.
Therefore, a great amount of power is consumed. If the comparison operation is performed on the memory cells of all the rows, the power consumption for the memory is extremely high. Such CAM apparatus is not applicable for the more and more commonly used low supply voltage apparatus.
SUMMARY OF THE INVENTION
The invention provides a content addressable memory (CAM) apparatus and a method of operating the CAM apparatus that can reduce the operation power consumption and production cost.
The CAM apparatus and the method of operating the same provided by the invention can process many CAM arrays in parallel, so that the operation efficiency is greatly enhanced.
The CAM apparatus comprises a memory array and a frequency multiplier. The memory array comprises a memory cell row, which further comprises a plurality of memory portions and a tag-compare portion. Each of the memory portions is used to store bit data. The tag-compare portion is used to receive a compare data signal, and to compare the compare data signal with the bit data stored in all the memory portions. The memory portions are connected to the tag-compare portion in parallel. The frequency multiplier is used to receive an external drive signal, and to output an internal compare signal after multiplying the drive signal with a certain numeric. The tag-compare portion sequentially compares the compare data signal with the bit data stored in each memory portion according to the clock of the internal compare signal, that is, the internal compare clock, and then outputs a match signal.
The above CAM apparatus comprises a plurality of word lines. Each of the word lines is connected to the memory portion corresponding to the memory cell row. Via the word lines, the electric connection between the memory portions and the tag-compare portion is attained according to the internal compare clock.
The above CAM apparatus further comprises a match register to receive and temporarily store the match signal.
The above CAM apparatus further comprises a match sense amplifier located between the memory cell row and the match register to sense and receive the match signal. The match sense amplifier then outputs the match signal, which is then amplified thereby.
In the above CAM apparatus, the memory portions in clude a static random access memory (SRAM). The SRAM comprises two transistors and a capacitor, or a transistor and a capacitor. With these two structures, the SRAM may further comprise a refresh line coupled to all the memory portions. Via the refresh operation, the data stored in the SRAM is maintained.
The invention further provides an operation method of the CAM apparatus. The CAM apparatus comprises at least a memory cell row, which comprises a plurality of memory portions and a tag-compare portion. The tag-compare portion receives a compare dat a signal. The operation method comprises receiving a drive signal and outputting an internal compare signal after multiplying the drive signal by a predetermined numeric. According the clock of the internal compare signal, the tag-compare portion sequentially compares the compare data signal and the bit data stored in each memory portion, and outputs a match signal.
In the above method, the CAM apparatus further comprises a plurality of word lines, each of which is connected to the memory portion corresponding to the respective memory cell row. Via the word lines, the electric connections between the memory portions and the tag-compare portion are attained according to the clock of the internal compare signal.
In the above method, the memory portions include a SRAM, which may comprises two transistors and a capacitor, or a transistor and a capacitor. With these two structures, the memory portions further comprise a refresh line coupled to all the memory portions. The data stored in the SRAM is retained by the refresh operation.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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Elms Richard
J.C. Patents
Nguyen Tuan T.
LandOfFree
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