Content-addressable memory

Details Content-addressable memory Content-addressable memory

1991-02-13

1993-11-02

Wambach, Margaret Rose

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518904, 36518907, 307201, 307530, 307464, H03F 345, H03K 1923

Patent

active

052589463

ABSTRACT:
A measure of the correlation or degree of closeness between an input data pattern and a stored data pattern is achieved directly from content-addressable memory cells which are realized in accordance with the principles of the present invention to provide a match
on-match output indication which is summable with other such match
on-match output indications on a match bus line for computing the correlation or degree of closeness measure. Each content-addressable memory cell includes a single bit, static random access memory cell and a comparing logic gate connected jointly to the output of the static random access memory cell and the bit bus line for the single bit of the input data pattern. Output of the comparing logic gate is connected to the match bus line and is generated as a fixed amount of current which can be summed with other current on the match bus line. The output stage of the comparing gate is thus operated as a current source. Each content-addressable memory cell accepts digital input signals and delivers a usable analog output signal. In one embodiment, the content-addressable memory cell is realized in a complementary metal oxide semiconductor technology and the comparing logic gate is an exclusive-NOR gate.

REFERENCES:
patent: 3633182 (1972-01-01), Koo
patent: 4780845 (1988-10-01), Threewitt
J. T. Koo, IEEE J. of Solid-State Circuits, Oct. 1970, "Integrated-Circuit Content-Addressable Memories", pp. 263-270.
T. Kohonen, Springer-Verlag 1980, pp. 199-203, "Content-Addressable Memories".
Clark et al., IEEE J. of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, "A Pipelined Associative Memory . . . ", pp. 28-34.
Ogura et al., IEEE J. of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, "A 20-kbit Associative Memory LSI . . . ", pp. 1014-1020.
J. P. Wade et al., IEEE J. of Solid-State Circuits, vol. 24, No. 4, Aug. 1989, "A Ternary Content Addressable Search Engine", pp. 1003-1013.
Graf et al., IEEE International Solid-State Circuits Conf., 1990, "A Reconfigurable CMOS Neural Network", pp. 144-145.

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