Content addressable memory

Details Content addressable memory Content addressable memory

1997-09-04

1999-08-24

Nguyen, Viet Q.

Static information storage and retrieval

Associative memories

Ferroelectric cell

3652385, 36518905, 365239, 365233, G11C 1500

Patent

active

059432527

ABSTRACT:
A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global data signal. This signal interacts with two major control signals to self-time the memory. The number of major control signals is such that all possible memory states are uniquely represented, but the memory cannot power-up in an invalid or unrecoverable state. Three model timing paths are used to match the delay of the self-timing loop with that of the actual operation: one each for READ, WRITE and SEARCH.

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