Static information storage and retrieval – Associative memories – Ferroelectric cell
Reexamination Certificate
2000-08-29
2001-08-14
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S200000
Reexamination Certificate
active
06275406
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory circuits, and more particularly to content addressable memory circuits having redundant arrays for replacing defective entries.
2. Description of the Related Art
Memory devices are indispensable components of modem computer systems. As storage devices, they are used to provide fast access to data and instructions stored therein. Content addressable memory (CAM) is a special type of memory that is often used for performing address searches. For example, Internet routers often include a CAM for searching the address of specified data. The use of CAMs allows the routers to perform address searches to allow computer systems to communicate data with one another over networks. Besides routers, CAMs are also utilized in other areas such as database searches, image processing, and voice recognition applications.
FIG. 1A
shows a block diagram of a conventional CAM
100
. The CAM
100
includes a CAM array
102
and a control block
104
. Additionally, the CAM
100
includes a data bus
106
for communicating data, an instruction bus
108
for transmitting instructions associated with an operation to be performed, and an output bus
110
for outputting a result of the operation. In a search operation, for example, the CAM
100
may output a result in the form of an address, pointer, or bit pattern corresponding to an entry that matches the input data.
In this configuration, the data bus
106
provides input data to the CAM array
102
while the instruction bus
108
provides CAM operation instructions to the control block
104
. In response to an instruction, the control block
104
generates control signals for controlling the operations of the CAM array
102
. At the end of a search operation, the CAM
100
outputs, on the result bus
110
, an address, pointer, or bit pattern (collectively referred herein as “address”) corresponding to an entry or word in the CAM array
102
that matches the input data on the data bus
106
. For a read operation, on the other hand, the CAM
100
outputs on the result bus
106
data corresponding to the address provided on the instruction bus
108
. CAMs are well known in the art and are described, for example, in U.S. Provisional Patent Applications, Nos. 60/153,388 and 60/167,155, which were previously incorporated by reference.
CAMs typically include a two-dimensional row and column content address memory array of core cells, such that each row contains an address, pointer, or bit pattern entry. Based on such array of cells, a CAM may perform “read ” and “write” operations at specific addresses like a conventional random access memory (RAM). In addition, it may also perform “search” operations that simultaneously compare a bit pattern of data against an entire list (i.e., column) of pre-stored entries (i.e., rows) of bit patterns in the CAM array.
However, CAMs often become inoperable or unusable due to one or more defective cells. For example, a cell may become defective during the manufacturing process or operation of the CAMs.
FIG. 1B
illustrates a more detailed block diagram of the CAM array
102
showing a defective cell
170
. The CAM array
102
includes a plurality of entries (e.g., rows, words)
152
,
154
,
156
,
158
,
160
,
162
, and
164
. Each of the entries includes a plurality of core cells (e.g., memory cells) for storing data bits. For example, the entry
160
includes a plurality of core cells
166
,
168
,
170
,
172
, and
174
, which are coupled to a match line (ml)
176
. The match line
176
is asserted when all cells on the entry
160
matches those of input data. Each of the cells
166
to
174
is coupled to a word line (wl) and a pair of bit and complementary bit lines (bl and blbar). A encoder
150
is coupled to receive one or more search results such as search addresses from the CAM array
102
. The encoder
150
then determines and outputs a search result having the highest priority. In the CAM array
102
, the defective cell
170
in the entry
160
renders the entire entry
160
unusable. This is because the entry
160
can no longer produce a reliable result on its match line
176
when any of its cells is defective.
To increase manufacturing yield, other memory technologies such as SRAM and DRAM have provided redundant memory to replace the defective memory entries. That is, the redundant memory is used to store the data in lieu of a defective entry. Such techniques have typically provide fuses for the row decoders. The fuses for the defective rows are then blown to disable the defective rows, thereby preventing access to the defective rows.
In CAMs, however, implementing redundant address is not as simple as blowing a fuse for a row decoder. Unlike conventional SRAMs and DRAMs, the CAM array is generally configured for efficient search operations that output one or more search addresses. In addition, CAMs typically include a encoder for outputting a search address from one or more search addresses. Implementing redundancy in a CAM requires an intelligent encoder that knows that a defective entry has been replaced by a redundant entry for proper operation of the CAMs.
Furthermore, modem CAM array sizes have been increasing at a steady pace. While a typical CAM array size is 256 Kbit, some CAM arrays are approaching the size of 2 to 4 Mbits, which represents a substantial increase in size. For example, in routers, the large CAM array size allows storage of larger tables. However, the larger table size results in more complex packet forwarding schemes. In such critical applications, when a single cell is found to be defective, the entire chip becomes useless. Such defects thus have the undesirable effect of reducing yield and driving up the cost of the CAM chips.
In view of the foregoing, what is needed is a CAM circuit and method that provide redundancy with transparent mapping scheme without requiring complex encoder, thereby enhancing the yield of CAM chips with attendant savings in cost.
SUMMARY OF THE INVENTION
The present invention fills this need by providing a CAM circuit having a redundant array and methods for implementing the same. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, the present invention provides a CAM circuit having a redundant array. The circuit includes a first CAM array, a redundant CAM array, one or more storage devices, a first encoder, and a redundant encoder. The first CAM array stores data and has a plurality of first entries. Each first entry has a plurality of first memory cells, wherein any first entry that includes one or more defective first memory cells is defective. The redundant CAM array has one or more redundant entries of redundant memory cells. Each of the one or more redundant entries has a redundant address and is associated with a defective first entry, wherein each redundant entry is configured to store data for the associated first entry. The one or more storage devices, preferably one or more fuse banks, associate each of the defective first entries with a redundant entry. The first encoder outputs a first search result from the first CAM array while the redundant encoder outputs a redundant search result from the redundant CAM array.
In another embodiment, a CAM circuit with redundancy includes a primary CAM array, a redundant CAM array, one or more storage devices, a primary encoder, and a redundant encoder. The primary CAM array stores data and includes a plurality of primary entries. The primary entries are addressable by a plurality of primary addresses that defines a primary address space with one primary address being provided for each primary entry. The redundant CAM array includes a set of redundant entries, which are addressable by a set of redundant addresses that defines a redundant address space. One redundant address is provided for each redundant e
Gibson G. F. Randall
Podaima Jason E.
Shafai Farhad
Le Vu A.
Martine & Penilla LLP
Phung Anh
SiberCore Technologies, Inc.
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