Contamination control for embedded ferroelectric device...

Details Contamination control for embedded ferroelectric device... Contamination control for embedded ferroelectric device...

2001-08-08

2004-03-23

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C438S240000

Reexamination Certificate

active

06709875

ABSTRACT:

TECHNICAL FIELD
This invention relates to systems and methods of controlling contamination during fabrication of embedded ferroelectric devices.
BACKGROUND
Today, several trends exist in the semiconductor device fabrication industry and the electronics industry that are driving the development of new material technologies. First, devices, such as personal handheld devices (e.g., cellular telephones and personal digital assistants) are continuously getting smaller and smaller and requiring less and less power. Second, in addition to being smaller and more portable, such devices are requiring more computational power and on-chip memory. In light of these trends, there is a need in the industry to provide a computational device that has a fair amount of memory and logic functions integrated onto the same semiconductor chip. Preferably, this computation device will include a non-volatile memory so that if the battery dies, the contents of the memory will be retained. Examples of conventional non-volatile memories include electrically erasable, programmable read only memories (“EEPROM”) and flash EEPROMs. Table 1 illustrates the differences between different memory types.
A ferroelectric memory (FeRAM) is a non-volatile memory that utilizes a ferroelectric material (e.g., SrBi
2
Ta
2
O
9
(SBT) or Pb(Zr,Ti)O
3
(PZT)) as a capacitor dielectric that is situated between a bottom electrode and a top electrode. In general, ferroelectric memory elements are non-volatile because of the bistable polarization state of the material. In addition, ferroelectric memory elements may be programmed with relatively low voltages (e.g. less than 5 volts) and are characterized by relatively fast access times (e.g. less than 40 nanoseconds) and operational robustness over a large number of read and write cycles. These memory elements also consume relatively low power, may be densely packed, and exhibit radiation hardness.
TABLE 1
FeRAM
Property
SRAM
Flash
DRAM
(Demo)
Voltage
>0.5 V
Read >0.5 V
>1 V
3.3 V
Write (12 V)
(±6 V)
Special Transistors
NO
YES
YES
NO
(High Voltage)
(Low Leakage)
Write Time
<10 ns
100 ms
<30 ns
60 ns
Write Endurance
>10
15
<10
5
>10
15
>10
13
Read Time (single/
<10 ns
<30 ns
<30 ns/<2
60 ns
multi bit)
ns
Read Endurance
>10
15
>10
15
>10
15
>10
13
Added Mask for
0
~6-8
~6-8
~3
embedded
Cell Size (F~metal
~80 F
2
~8 F
2
~8 F
2
~18 F
2
pitch/2)
Architecture
NDRO
NDRO
DRO
DRO
Non volatile
NO
YES
NO
YES
Storage
I
Q
Q
P
To integrate ferroelectric capacitors with standard complimentary metal oxide semiconductor (CMOS) device technology, several new materials with non-standard metal constituents must be introduced into the Si wafer fabrication facility. Among the materials that are needed to fabricate a typical ferroelectric capacitor stack are PZT or SBT dielectrics, along with one or more of the following electrode materials: Ir, Ru, or Pt. Some of the metals present in these materials, such as Ti, Ta, and Pt, are used in mainstream Si wafer fab lines. Other metals, such as Pb, Zr, Sr, Bi, Ru, and Ir, conventionally are not introduced into Si manufacturing flows. Accordingly, little is known regarding the effect of these materials on the yield, reliability, and electrical performance of CMOS-based devices. Moreover, despite the fact that front-end technology requirements for wafer surface processing stipulate concentrations less than 9×10
9
atoms/cm
2
for known critical metals such as Cu at the 180 nm technology node, precise limits for the FeRAM-related metal contaminants have not been quantified.
SUMMARY
In general, the invention relates to the creation of ferroelectric capacitors in a FeRAM process module that occurs between a front-end process module (that includes, e.g., logic and contact processes) and a backend process module (that includes, e.g., mostly metallization processes). The FeRAM process module should be compatible with the front-end process flow including the use of W contacts, which currently are standard in most logic flows, as the bottom contact of the capacitor. The FeRAM thermal budget also should be low enough that it does not impact low resistance structures in the front end (such as tungsten plugs and silicided source/drains and gates) that are used in most logic devices. In addition, since transistors and other front-end devices (e.g., diodes) are sensitive to contamination, the FeRAM process module should not contaminate such devices either directly (e.g., by diffusion in chip) or indirectly (e.g., by cross contamination through shared equipment). The FeRAM devices and process module also should be compatible with standard backend process flows. Accordingly, the FeRAM process module should not increase the resistance of the logic metallization and should not increase parasitic capacitances between metal and transistor. In addition, the FeRAM devices should not be degraded by standard backend process flows. This is a significant challenge since ferroelectric capacitors have been shown to be sensitive to hydrogen-induced degradation and most logic backend processes use hydrogen or deuterium (e.g. SiO
2
, Si
3
N
4
, and CVD W deposition, SiO
2
via etch, and forming gas anneals).
With respect to contamination control, the level of contamination in substrates that are processed through shared equipment (e.g., steppers or metrology tools) should not be high enough to degrade device performance. Aside from processing errors, a primary route for cross-contamination is contact between wafer handling systems in shared tools and the backside, edge, and frontside edge exclusion zone surfaces of the substrate. In the case of a typical FeRAM process flow, two processes are expected to lead to the most severe contamination of the wafer backside and edge: (1) deposition of the PZT or SBT film, and (2) dry etching of the ferroelectric capacitor stack. Thus, in order to achieve the production efficiencies resulting from the use of shared equipment and shared process facilities, undesired elements should be removed from the substrate backside, edge, and frontside edge exclusion zone prior to the use of any shared process equipment.
In one aspect, the invention features a method of forming a ferroelectric device on a substrate having a top surface, a bottom surface, an edge and a frontside edge exclusion zone. In accordance with this method, a bottom electrode is formed over the top surface of the substrate. A ferroelectric dielectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric dielectric layer. To control contamination, ferroelectric device material (e.g., ferroelectric-related contamination, such as Pb, Zr, Ti, and electrode-related contamination, such as Ir) is etched selectively from the substrate bottom surface and edge.
Embodiments of the invention may include one or more of the following features.
Ferroelectric device material preferably is etched selectively from the substrate bottom surface and edge with an etchant comprising an acid containing fluorine or an acid containing chlorine, or both. In one embodiment, the etchant includes a mixture of NH
4
F and HCl. The etchant may include a NH
4
F:HCl volume ratio of about 1.6. The etchant may further include a diluent (e.g., H
2
O). In one embodiment, the etchant comprises a NH
4
F:HCl:H
2
O volume ratio of about 1:1.6:x, wherein x preferably has a value ranging from about 20 to about 1,000 and, more preferably, has a value ranging from about 40 to about 100.
In other embodiments, ferroelectric device material is etched selectively from the substrate bottom surface, edge and frontside edge exclusion zone with an etchant comprising a mixture selected from the following: HCl and H
2
O; HF and H
2
O; HNO
3
and H
2
O; HF, HCl and H
2
O; NH
4
F, HCl, HNO
3
and H
2
O; HF, HCl, HNO
3
and H
2
O; and HF, H
2
O
2
, HNO
3
and H
2
O.
Ferroelectric device material also may be etched selectively from the substrate frontside edge exclusion zone.
In some embodiments, the substrate comprises a sacrificial layer disposed

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