Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-03-16
2002-12-10
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090
Reexamination Certificate
active
06492829
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device having an interconnection substrate and semiconductor integrated circuits located on the interconnection substrate, and an inspection contactor for inspecting the electrical continuity of a wafer to be inspected.
Hitherto, in order to realize with a low cost a semiconductor device or system LSI with high-degree, complicated functions by use of flip chip bonding in which a plurality of LSI chips are directly mounted on an interconnection substrate, a bump connection system using bumps formed of solder or metal is used as a mounting method for mounting, after independently producing chips each having a function such as micro-computer or memory etc., the produced chips on the interconnection substrate at a high density.
However, in the bump connection system using the bumps formed of the solder or metal, there is such a problem as thermal strain occurs in the bumps etc. due to difference in thermal expansion coefficient between the LSI chips and the interconnection substrate with the result that fatigue fracture occurs in the bumps etc.
As means for preventing this problem from occurring, there is a method in which a gap defined between the LSI chip and the interconnection substrate is filled with an epoxy type thermosetting resin in which fine particles (usually called “filler”) such as glass particles etc. are included, so that thermal warp between the LSI chip and the interconnection substrate may be restrained, whereby thermal stress occurring in the metal bumps etc. are reduced to thereby improve the connection reliability of the metal bumps etc.
Further, a method disclosed in JP-A-10-270496 (a mounting method usually called “underfill structure”) is known in which an anisotropic, conductive resin is used as the epoxy type thermosetting resin in which fine particles such as glass particles etc. are included. Or, as a method of realizing the system LSI, there is known a method comprising the steps of: arranging a plurality of chips, which are individually produced previously, on an identical plane; and then electrically connecting the chips to each other by use of thin film interconnection technique.
However, in the conventional methods explained above, there are such problems as a step of filling with resin is necessary after mounting the LSI chips on the interconnection substrate with the result that a production cost thereof becomes high, and as, in a case where troubles such as defective chip etc. are found in the reliability test etc. after the assembling thereof, the filled resin must be removed to exchange the defective LSI chip with the result that much labor is required.
Further, in a case where LSI chips are mounted at a high density, it becomes indispensable, due to the increase of generated-heat occurrence density of the whole of a device, to provide a heat-dissipating mechanism for improving the heat dissipation of the whole device, which impedes the small size design of the device.
In addition, in a case of using a bonding method other than the above method using the solder bumps, it is necessary to perform with high precision the alignment between a LSI chip and electrode pads located on an interconnection substrate, which has been an obstacle to the simplification of operations for mounting the LSI chip on the substrate.
SUMMARY OF THE INVENTION
The object of the invention is to obtain a semiconductor device and an inspection contactor both superior in heat dissipation in each of which a plurality of LSI chips are mounted on an interconnection substrate having substantially no difference in thermal expansion coefficient between the LSI chips and the substrate by use of means distinct from conventional bonding or connecting, whereby the exchange or mounting of the chips can be readily performed.
According to the first aspect of the invention, there is provided a semiconductor device comprising:
an inner cover made of a material containing silicon as the main constituent thereof in which inner cover LSI chips each provided with semiconductor integrated circuits are located;
an interconnection substrate made of a material containing silicon as the main constituent thereof and connected to the inner cover, the substrate being provided on the surface thereof with electrode terminals each formed to have a pyramid-like shape at a portion of a cantilever which electrode terminals are electrically in contact with the LSI chips, an interconnection layer connected to the electrode terminals, and electrodes for performing electrical connection to exterior portions which electrodes are connected to the interconnection layer, and
an outer cover made of a metal other than silicon or a macromolecular material which outer cover covers the inner cover and the interconnection substrate.
Preferably, in the first aspect of the invention, the interconnection substrate and the inner cover are connected to each other through fitting portions.
According to the second aspect of the invention, there is provided a semiconductor device comprising:
a first inner cover made of a material containing silicon as the main constituent thereof in which is located at least one LSI chip provided with semiconductor integrated circuits;
a second inner cover made of a material containing silicon as the main constituent thereof in which is located at least one LSI chip provided with semiconductor integrated circuits;
an interconnection substrate made of a material containing silicon as the main constituent thereof, the substrate being provided on one face thereof with electrode terminals each formed to have a pyramid-like shape in a portion of a cantilever which electrode terminals are in electrical contact with the LSI chip located in the first inner cover, a first interconnection layer connected to the electrode terminals, and electrodes connected to the first interconnection layer which electrodes perform electric connection to exterior portions, the substrate being further provided on the other face thereof with electrode terminals each formed to have a pyramid-like shape in a portion of a cantilever which electrode terminals are in electrical contact with the LSI chip located in the second inner cover, a second interconnection layer connected to the electrode terminals formed on the other face of the substrate, and a third interconnection layer for connecting the first interconnection layer to the second interconnection layer, the one face of the interconnection substrate being connected to the first inner cover, the other face of the interconnection substrate being connected to the second inner cover; and
an outer cover made of a metal different from silicon or a macromolecular material which outer cover covers the first inner cover, the second inner cover and the interconnection substrate.
Preferably, in the second aspect of the invention, the interconnection substrate, the first inner cover and the second inner cover are connected to each other through fitting portions.
According to the third aspect of the invention, there is provided a semiconductor device comprising:
a first inner cover made of a material containing silicon as the main constituent thereof in which is located at least one LSI chip provided with semiconductor integrated circuits;
a second inner cover made of a material containing silicon as the main constituent thereof in which is located at least one LSI chip provided with semiconductor integrated circuits;
a silicon cover with an interconnection substrate, the substrate being provided on one face thereof with electrode pads, electrode terminals each formed to have a pyramid-like shape in a portion of a cantilever which electrode terminals are in electrical contact with the electrode pads, and at least one LSI chip having semiconductor integrated circuits, the substrate being further provided on the other face thereof with electrode terminals each formed to have a pyramid-like shape in a portion of a cantilever which electrode terminals are in electrical contact with the LSI chip located in the second
Kohno Ryuji
Miura Hideo
Antonelli, Terry Stout & Kraus, LLP.
Hitachi , Ltd.
Karlsen Ernest
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