Contactless uniform-tunneling separate p-well (CUSP)...

Details Contactless uniform-tunneling separate p-well (CUSP)... Contactless uniform-tunneling separate p-well (CUSP)...

2002-08-29

2003-11-18

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Rendering selected devices operable or inoperable

C438S005000, C438S010000, C438S017000, C438S466000, C365S145000

Reexamination Certificate

active

06649453

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory cells and in particular the present invention relates to flash memory cells.
BACKGROUND OF THE INVENTION
Memory devices are available in a variety of styles and sizes. Some memory devices are volatile in nature and cannot retain data without an active power supply. A typical volatile memory is a DRAM which includes memory cells formed as capacitors. A charge, or lack of charge, on the capacitors indicate a binary state of data stored in the memory cell. Dynamic memory devices require more effort to retain data than non-volatile memories, but are typically faster to read and write.
Non-volatile memory devices are also available in different configurations. For example, floating gate memory devices are non-volatile memories that use floating gate transistors to store data. The data is written to the memory cells by changing a threshold voltage of the transistor and is retained when the power is removed. The transistors can be erased to restore the threshold voltage of the transistor. The memory may be arranged in erase blocks where all of the memory cells in an erase block are erased at one time. Such non-volatile memory devices are commonly referred to as flash memories.
The non-volatile memory cells are fabricated as floating gate memory cells and include a source region and a drain region that is laterally spaced apart from the source region to form an intermediate channel region. The source and drain regions are formed in a common horizontal plane of a silicon substrate. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by a dielectric. For example, a gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and is can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is “floating” in dielectric so that it is insulated from both the channel and the control gate.
As semiconductor devices get smaller in size, designers are faced with problems associated with the production of memory cells that consume a small enough amount of surface area to meet design criteria, yet maintain sufficient performance in spite of this smaller size.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative memory device architectures.
SUMMARY
The above-mentioned problems with non-volatile memory cells and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The various embodiments relate to non-volatile semiconductor memory cells, arrays, as well as their fabrication and architecture. Such memory cells can use Fowler-Nordheim (FN) tunneling during both program and erase operations while maintaining random access capabilities. Due to the nature of FN tunneling, the memory cells can operate at relatively low power consumption. Additionally, because of the low power consumption of FN tunneling compared to hot-electron processes, many, e.g., thousands, of cells may be programmed or erased in parallel. While parallel programming and erase operations are suitable for large blocks of memory cells, cells may be programmed or erased individually while still facilitating a smaller cell size than a typical electrically-erasable programmable read-only memory (EEPROM).
For one embodiment, the invention provides an array of floating-gate field-effect transistors. The array includes two or more columns of the floating-gate field-effect transistors, each field-effect transistor of a column sharing a first source/drain region and a second source/drain region with other field-effect transistors of that column. The first and second source/drain regions of a column are contained in a first well having a first conductivity type. The first well for each column is isolated from first wells of other columns.
For another embodiment, the invention provides a method of erasing a memory cell in an array of memory cells. The method includes applying a first potential to a word line associated with the memory cell, applying a second potential to a first source/drain region and a second source/drain region of the memory cell, and applying the second potential to a first well containing the first and second source/drain regions. The method further includes applying a third potential to a second well. The second well is underlying the first well and is coupled to the first well through a PN junction.
For yet another embodiment, the invention provides a method of programming a memory cell in an array of memory cells. The method includes applying a first potential to a word line associated with the memory cell, applying a second potential to a first source/drain region and a second source/drain region of the memory cell and applying a third potential to a first well containing the first and second source/drain regions. The method further includes applying the third potential to a second well underlying the first well. The second well is coupled to the first well through a PN junction and the third potential has the second polarity.
For still another embodiment, the invention provides a non-volatile memory device. The memory device includes an array of non-volatile floating-gate memory cells arranged in rows and columns and control circuitry for controlling access to the array of memory cells. Each column of memory cells shares a source and a drain, the source and drain for a column of memory cells being contained in a first well associated with that column of memory cells. The first well associated with each column of memory cells is isolated from other first wells of other columns of memory cells. Each first well is overlying a second well in a many-to-one relationship and each first well has a first conductivity type. The second well has a second conductivity type different than the first conductivity type.
Further embodiments of the invention include methods and apparatus of varying scope.


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