Contactless testing of inputs and outputs of integrated circuits

Details Contactless testing of inputs and outputs of integrated circuits Contactless testing of inputs and outputs of integrated circuits

1996-06-28

1997-06-24

Canney, Vincent P.

Excavating

371 223, 39518306, G06F 1100

Patent

active

056423640

ABSTRACT:
A test circuit for an integrated circuit by which electrical parameters of input/output (I/O) circuits of the integrated circuit are tested without direct electrical contact to the I/O, including a an output buffer Vdd supply bus (31) and an output buffer Vss return bus (32) for providing Vdd and Vss voltages for drivers of output buffers (41) of the I/O circuits of the integrated circuit; an interior logic Vdd supply bus (25) and an interior logic Vss return bus (26) for providing Vdd and Vss voltages for the interior logic (10) of the integrated circuit and the input buffers (45) of the I/O circuits; and a pull up Vdd supply bus (23) and a pull down Vss return bus (24) for providing Vdd and Vss voltages for the pull up sources (47) and the pull down sources (49) of the I/O circuits. Also disclosed is a self-shorting output buffer.

REFERENCES:
patent: 5404358 (1995-04-01), Russell
patent: 5544309 (1996-08-01), Chang et al.

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