Contactless non-volatile memory array cells

Details Contactless non-volatile memory array cells Contactless non-volatile memory array cells

1989-01-06

1992-05-12

Hille, Rolf

357236, 357 45, H01L 2934, H01L 2968, H01L 2710

Patent

active

051132389

ABSTRACT:
A non-volatile MOS memory array cell in which polycide bit lines are connected via self-aligned buried contacts to shared drain regions and run continuously over, but are electrically isolated from, shared source regions. Self-aligned buried contact windows are obtained by depositing and anisotropically etching-back an oxide layer with a non-critical mask. Preferably N-type doped polycide provides bit lines and self-aligned buried contacts with low resistance, low current leakage to the substrate, and good step coverage without bit line bridging. It is expected that this invention will make it feasible to manufacture high density non-volatile memory array products with good yield rates.

REFERENCES:
patent: 4094057 (1978-06-01), Bhattacharyya
patent: 4475964 (1984-10-01), Ariizumi
patent: 4649406 (1987-03-01), Takemae
patent: 4698787 (1987-10-01), Mukerjee

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