Contactless flash memory with buried diffusion bit/virtual...

Details Contactless flash memory with buried diffusion bit/virtual... Contactless flash memory with buried diffusion bit/virtual...

2001-04-20

2003-05-27

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S185110

Reexamination Certificate

active

06570810

ABSTRACT:

BACKGROUND
A conventional contactless Flash memory array employs bit lines and source lines that are diffused into a silicon substrate.
FIG. 1A
conceptually illustrates the layout of part of a bank
100
in a conventional contactless Flash memory. In bank
100
, n+ diffusion into a silicon substrate forms diffused bit lines
110
and diffused source (or ground) lines
120
. Polysilicon floating gates
130
(poly
1
) overlie channel regions, which are between diffused bit lines
110
and diffused source lines
120
. Polysilicon word lines
140
(poly
2
) cross over portions of diffused bit lines
110
and diffused source lines
120
that form the drains and sources of memory cells and also overlie associated floating gates
130
.
FIG. 1B
shows a cross section along a word line
140
in bank
100
. As shown in
FIG. 1B
, channel regions
115
in the silicon substrate separate drain regions of diffused bit lines
110
from source regions of diffused source lines
120
. Floating gates
130
overlie respective channel regions
115
, with a gate insulator (e.g., gate oxide layer) between floating gates
130
and underlying channel regions
115
. Word lines
140
overlie floating gates
130
with an insulating layer between each word line
140
and the underlying float gates
130
that are in a row corresponding to the word line.
Isolation structures
125
such as shallow trench isolation (STI) regions, conventional field oxide (LOCOS) regions, or heavily doped p+ field implant regions separate adjacent diffused lines
110
from each other. Similar isolation structures (not shown) also separate adjacent channel regions
115
from each other.
As shown in
FIG. 1A
, each diffused bit line
110
extends to an associated bank select cell
170
. Bank select cells
170
include transistors between respective diffused bit lines
110
and contacts to respective metal bit lines
180
that are typically part of a first metal layer and that overlies corresponding diffused bit lines
110
. Generally, each metal bit line
180
extends over a number of banks and is connected to a corresponding select cell in each of the banks. A bank select line
160
controls bank select cells
170
in the bank to determine whether diffused bit lines
110
in the bank are connected to respective metal bit lines
180
.
Diffused source lines
120
extend to contact virtual ground devices (not shown) or to other structures for control of the voltages of diffused source lines
120
during erase, write, and read operations.
A memory cell
150
in bank
100
of
FIG. 1A
includes a single floating gate transistor, and the number of memory cells in bank
100
is equal to the number of floating gates
130
. In operation, charge added to or removed from the floating gate
130
in a memory cell
150
during a program or erase operation changes the threshold voltage of the floating gate transistor in the memory cell
150
. The binary value stored in a memory cell
150
depends on whether the memory cell
150
is in a state having a high threshold voltage or a low threshold voltage.
The layout of each memory cell
150
in the contactless Flash memory array of
FIG. 1A
includes areas for a floating gate transistor and surrounding isolation structures. To minimize the area of a memory cell, features in the memory cells have widths or lengths equal to the minimum feature size, f, permitted by the design rules governing manufacture of the Flash memory integrated circuit. Along the direction perpendicular to diffused bit lines
110
, the features for a memory cell include a shared isolation structure
125
, a drain region of diffused bit line
110
, a channel region
115
, and a shared source region of diffused source line
120
as illustrated in FIG.
1
B. The width and length of each of these structures are at least as wide or long as the minimum feature size f. Accordingly, a memory cell has an overall length (counting half the size of the shared features
120
and
125
) of about 3f. The overall width of the memory cell area includes the width of the associated word line
140
and half of the widths of two adjacent isolation structures or at least 2f. The minimum memory cell area is thus about 6f
2
(3f×2f).
The effective memory cell size for bank
100
must additionally include a pro-rata portion of integrated circuit area associated with required overhead circuitry such as bank select cells
170
, source contacts (not shown), and any virtual ground structures. More specifically, in one architecture M cells on a diffused bit line
110
share one bank select cell
170
, the effective size of each memory cell is greater than 6f
2
by 1/M times the area of a bank select cell and any other overhead for the column.
A contactless memory architecture that reduces the required cell area could increase the storage density achieved in a Flash memory integrated circuit (IC) and could therefore decrease the cost of Flash memory ICs.
SUMMARY
In accordance with an aspect of the invention, a contactless memory architecture has diffused lines that operate either as diffused bit lines or diffused source lines depending on the voltage through bank select cells to the diffused lines. Word lines crossing the diffused lines have underlying floating gates and channel regions between each pair of adjacent diffused lines, and no isolation structures are required between adjacent diffused lines. Elimination of these isolation structures significantly reduces the minimum cell area and permits a higher density of memory cells within a bank.
In the exemplary embodiment, each bank includes two sets of bank select cells, typically at opposite ends of the diffused lines. Each bank select cell except some corresponding to diffused lines at edges of a bank connect an associated metal line to a pair of diffused lines. One set of bank select cells connects the metal lines to pairs of diffused lines that are shifted relative to the pairs of diffused lines that the other set of bank select cells connect to the metal lines. For any pair of adjacent diffused lines, activating one set of the bank select cells connects both of the adjacent diffused lines to the same metal line, and activating the other set of the bank select cells connects the two adjacent diffused lines to different metal lines.
The metal lines act either as bit lines or as ground lines depending on which column of memory cells an access operation selects. The layout of the metal lines across a set of banks generally includes a zigzag pattern to accommodate the relative shift of the bank select cells at opposite ends of each bank, but other layouts are possible.
An access to a memory cell in a selected column biases metal lines to one side (e.g., the left) of a selected column of memory cells at a first voltage and biases metal lines on the other side (e.g., to the right) of the selected column of memory cells at a second voltage. The appropriate set of bank select cells is activated for the access to achieve a voltage difference between the pair of adjacent diffused lines associated with the selected column. The resulting drain/source voltage difference of the memory cells in the selected column permits access of the selected memory cell in the selected column, and the common voltages on all other pairs of adjacent diffused lines prevent access or significant disturbance of memory cells in unselected columns.
One embodiment of the invention is a bank of a memory such as a Flash memory. The bank includes memory cells arranged in rows and columns. Each memory cell includes a channel region in a substrate, a floating gate overlying the channel region, and a control gate overlying the floating gate. Diffused lines in the bank have portions that form source/drain regions of the memory cells, and every area of the substrate that is between an adjacent pair of the diffused lines contains the channel regions of memory cells that form a column in the bank.
The bank can additionally include first bank select cells and second bank select cells. Each first bank select cell includes a tr

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