Contactless array configuration for semiconductor memories

Details Contactless array configuration for semiconductor memories Contactless array configuration for semiconductor memories

1995-04-21

1999-12-28

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36518515, 36518516, G11C 1134

Patent

active

060090138

ABSTRACT:
The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

REFERENCES:
patent: 4503519 (1985-03-01), Arakawa
patent: 4608591 (1986-08-01), Ipri et al.
patent: 4794565 (1988-12-01), Wu et al.
patent: 4821236 (1989-04-01), Hayashi et al.
patent: 5042009 (1991-08-01), Kazerounian et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5212541 (1993-05-01), Bergemont
patent: 5280446 (1994-01-01), Ma et al.
patent: 5284784 (1994-02-01), Manley
IEDM, 1988, R. Kazerounian et al., "A 5 Volt High Density Poly--Poly Erase Flash EPROM Cell," IEEE (p.436).
IEDM, 1987, H. Kume et al., "A Flash-Erase EEPROM Cell with an Asymmetric Source and Drain Structure," IEEE (p. 560).
IEDM, 1986, A.T. Wu et al., "A Novel High-Speed 5-Volt Programming EPROM Structure with Source-Side Injection," IEEE (p. 584).
IEDM, 1980, Masashi Wada et al., "Limiting Factors for Programming EPROM of Reduced Dimensions," IEEE (p. 38).
Dec., 1987, IEEE Transactions on Electron Devices, vol. ED-34, No. 12, Prall et al., "Characterization and Suppression of Drain Coupling in Submicrometer EPROM Cells" (p. 2463).
European Search Report for corresponding application BE 9100091 bearing the date "Oct. 08, 1991."
1993, Nonvolatile Memory Technology Review, J. Van Houdt, et al., "A 5v/3.3V-Compatible Flash E.sup.2 PROM Cell with a 400ns/70.mu.s Programming Time for Embedded Memory Applications," IEEE (p. 54).
Dec. 1993, IEEE Transactions on Electron Devices, vol. 40., No. 12, Jan Van Houdt et al., HIMOS--A High Efficiency Flash E.sup.2 PROM Cell for Embedded Memory Applications (p. 2255).
Sep. 1994, IEEE Transactions on Components, Packaging, and Manufacturing Technology--Part A, vol. 17, No. 3, Jan Van Houdt et al., "A 5 V-Compatible Flash EEPROM Cell with Microsecond Programming Time for Embedded Memory Applications" (p. 380).
Sep. 13-16, 1993, 23rd European Solid State Device Research Conference, Failure Physics and Analysis, Jan Van Houdt et al., "Optimization of a Submicron HIMOS Flash E.sup.2 PROM Cell for Implementation in a Virtual Ground Array Configuration," pp. 381-384.
Oct. 4-7, 1994, 5th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, D. Wellekens et al., "Write/Erase Degradation and Disturb Effects in Source-Side Injection Flash EEPROM Devices".
Esquivel, J. et al., "High Density Contactless, Self Aligned EPROM Cell Array Technology," IEEE, 1986, p. 592.
GIll, M. et al., "A 5-Volt Contactless Array 256KBit Flash EEPROM Technology," IEEE, 1988, p. 428.

Affiliated with

Also associated with

Rating

Contactless array configuration for semiconductor memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Contactless array configuration for semiconductor memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contactless array configuration for semiconductor memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2386695