Contactless array configuration for semiconductor memories

Details Contactless array configuration for semiconductor memories Contactless array configuration for semiconductor memories

1995-04-21

1998-11-24

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular connection

36518515, 36518516, G11C 1134

Patent

active

058416978

ABSTRACT:
The present invention relates to the field of electrically erasable and programmable nonvolatile semiconductor memories (EEPROM) and, in particular, to contactless array configurations that are used for the practical and efficient implementation of a particular type of memory transistor. Such a memory transistor allows fast 5 V-only programming by the use of an enhanced source-side injection mechanism. This concept requires a program gate in the field oxide region which serves to capacitively couple a high voltage to the floating gates. Thus, a very high injection current is established during programming. This additional program gate, however, increases the cell area considerably. The present disclosure shows a contactless 5 V-only Flash EEPROM array configuration that relies on shared program lines in order to minimize the area overhead that is caused by this program gate. Furthermore, a memory array with shared wordlines is presented which further enhances the density achievable.

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