Contactless annealing process using cover slices

Details Contactless annealing process using cover slices Contactless annealing process using cover slices

1987-11-19

1989-05-16

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437161, 437168, 437169, 437934, 148DIG3, H01L 21324

Patent

active

048309877

ABSTRACT:
The disclosure relates to a process for performing processing steps at elevated temperatures on semiconductor devices while minimizing outdiffusion of arsenic therefrom wherein an arsenide containing semiconductor cover wafer is etched to form a flange on the periphery thereof, the cover wafer being placed over the active region of an arsenide containing wafer being processed to form a substantial seal therewith with the active region being spaced from the cover wafer. The wafers are then heated to elevated temperature with outdiffused arsenic being retained in the space between the wafers to raise the arsenic vapor pressure thereat and minimize arsenic outdiffusion thereby. As alternate embodiments, plural wafers being processed and cover wafers can alternately be stacked, one over the other. A further alternate embodiment comprises coating the surface of the cover wafer to avoid contamination of the production wafer with impurities which may exist in the cover wafer.

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Armiento et al., "Capless Rapid Thermal Annealing of Grafts Using Enhanced Overprenune Proximity Technique", Appl. Phys. Lett., 48(23), 9 Jun. 1986, pp. 1623-1625.

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