Contact vias in semiconductor devices

Details Contact vias in semiconductor devices Contact vias in semiconductor devices

1985-11-15

1988-03-22

James, Andrew J.

Metal treatment

Stock

Ferrous

357 233, 357 52, 357 54, 148DIG133, H01L 2348, H01L 2944, H01L 2960

Patent

active

047332913

ABSTRACT:
A glass reflow step to round off sharp edges of contact vias is typically included in processes for making integrated-circuit devices. In the course of making such devices with closely spaced vias, it has been found that unacceptable overhangs occur on the sidewalls of the vias. Neither changes in the composition of the glass nor modifications in the processing parameters of reflow were effective to avoid the overhang phenomenon. In accordance with the invention, it has been discovered that the overhang problem can be consistently avoided if the ratio of glass thickness to via-to-via spacing is about .ltoreq.0.393.

REFERENCES:
patent: 3925572 (1975-12-01), Naber
patent: 4192059 (1980-03-01), Khan et al.
patent: 4535528 (1985-08-01), Chen et al.
patent: 4644386 (1987-02-01), Nishizawa et al.

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