Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-07-26
2002-01-08
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB, C324S538000, C324S754090
Reexamination Certificate
active
06337573
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to assuring that there is electrical contact between test probes and input/output pads of an integrated circuit device, prior to testing of the functional characteristics of the integrated circuit. More specifically, the invention relates to an apparatus and method for determining whether there is electrical contact between test probe and pad where the tester has no power supply more negative than the most negative power supply rail of the circuit being tested, and where the test current must flow through electrostatic discharge (ESD) diodes whose polarity requires that a contact test signal more negative than the most negative rail of the circuit under test be applied by the probe to the pad.
2. Background Description
When a tester is to be used to test integrated circuits on a wafer, all tester probes must be aligned exactly with the wafer I/O pads to assure meaningful tests. A group of the I/O pads may be devoted to one of many dice on the wafer in order to test the functionality of that particular die. More than one die may be tested at a time by allocating other groups of I/O pads to individual dice. Each good die ultimately will be packaged and sold as a unit. Throughout the following discussion, each die will be referred to as a DUT (device-under-test.) The rapid and simultaneous contact alignment verification of hundreds or thousands of test probes per wafer is a substantial contributor to DUT test time reduction and the concomitant reduction in price per good DUT. The trend toward larger wafers with increased pad densities makes automatic alignment sensing and verification a very desirable tester feature.
During contact alignment verification between test probes and wafer or DUT I/O pads, it is preferred to determine the validity of the connection by measuring an electrical response, such as input impedance, directly on the pad with no dependency on circuits residing interior to the DUT I/O. Such a contact test method should exploit existing DUT pads and I/O devices that serve the intended DUT I/O function, and should not require special I/O pads nor other devices devoted exclusively to contact alignment verification. The contact test method should be independent of internal DUT errors or failures.
There is a limited set of devices on the typical DUT that lend themselves to simple impedance analysis. Many of the I/O pads connect to gates of FETs which have a fundamentally capacitive impedance. It would be difficult to distinguish between the capacitive impedance of a FET gate and the capacitance of I/O wiring. Thus FET gates do not represent a practical impedance to use for contact verification. The impedance at these I/O pads is so high that there is a considerable risk that electrostatic voltages incurred during normal DUT handling will be large enough to break down the gate oxide and render the DUT useless. To dissipate these potentially destructive voltages, ESD diodes are connected in parallel with most I/Os on the DUT in either of two configurations. If only one ESD diode is used at an I/O pad, it is connected to conduct to the most negative rail when an ESD event drives the I/O pad negative with respect to the most negative rail of the DUT. If a second ESD diode is used, it is connected to conduct to the most positive rail when an ESD event drives the I/O pad positive with respect to the most positive rail of the DUT. The ESD diodes are the most commonly expected DUT I/O structures that are simple to measure as two terminal impedances. It is common practice to use ESD diodes for contact alignment verification.
Previous methods used for contact test most commonly depended on an ESD diode from the I/O pad to the negative rail of the DUT, and a power supply in the tester that was more negative than the most negative rail in the DUT. For each test probe that made proper contact, a direct current from the negative supply passed through that probe to the contacted DUT I/O pad, then through one or more corresponding ESD protection diodes on the DUT to the return path of the negative supply. If a test probe did not make contact, there was no current through the probe. The tester used the presence of current in each probe as an indication that contact was made through the implied impedance of one or more ESD diodes. The polarity of the ESD diodes imposed the requirement for a contact test signal from the tester that was more negative than the most negative rail of the DUT. Previous contact test circuits have used a current that is constant (dc) throughout the duration of contact test.
Often the only reason for the more negative power supply is for use in contact test. If the tester-to-DUT interface is comprised of integrated circuits (ICs) that normally require no negative power supply, the most negative power supply rail used by the tester ICs (often ground) must be connected temporarily to a negative supply to generate a negative dc contact test signal for the ESD diodes. The temporary connection may be made by means of a relay or switch. Once contact test is complete, the negative rail of the tester is restored to ground during functional testing of the wafer or DUT.
The necessity for switching the most negative rail of the tester to a more negative supply during contact test, then back to its normal value, slows DUT testing and may introduce objectionable impedance into the negative rail connection. It is desirable that any probe contact test and alignment verification method should avoid such switching.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a contact test circuit for ICs which operates without a power supply that is more negative than the most negative rail of the DUT.
It is also an object of the invention to provide a contact test circuit which operates without switches or relays.
It is a further object of the invention to provide a contact test circuit which can be used on DUTs without having to temporarily connect the most negative rail of the tester to a power supply more negative than the most negative rail of the DUT during contact test.
It is another object of the invention to provide a means for verifying the simultaneous alignment of multiple test probes.
It is an additional object of the invention to provide information on the condition of the DUT ESD diodes at each pad and indicate which probes might be shorted to ground.
It is also an object of the invention to provide automatically, either sequentially or simultaneously, for alignment and verification of multiple test probes.
Another object of the invention is to distinguish between probes that are shorted to ground, open, or connected to I/O pads of the DUT.
A further object of the invention is to distinguish between ESD diodes that are shorted, open or functioning properly.
It is also an object of the invention to distinguish between ESD diodes that are connected to ground or connected to the DUT power supply.
It is an additional object of the invention to accommodate different ESD diode specifications.
Another object of the invention is to provide protection against excessive current in probes that are improperly connected.
A further object of the invention is to provide low power dissipation through the ESD diodes.
It is also an object of the invention to provide isolation between contact test and tester data drivers on I/O.
A contact test circuit in accordance with the invention does not evaluate the current through DUT ESD diodes directly as dc. Instead the invention simulates a mini-ESD event at each I/O pad by means of a negative-going pulse, then stores as a voltage on a capacitor information about the history of events that took place during contact test as the result of the presence or absence of DUT ESD diodes. Evaluation of the resulting response of the test circuit occurs after the mini-ESD event is complete.
By this means, evaluation can be performed on voltages that are positive with respect to ground and no negative power supply is required to
Bonaccio Anthony R.
Leighton Howard J.
Chadurjian Mark F.
McGuireWoods LLP
Nguyen Trung Q.
Nguyen Vinh P.
LandOfFree
Contact test circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Contact test circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact test circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2837984