Contact structure for vertical chip connections

Details Contact structure for vertical chip connections Contact structure for vertical chip connections

1995-11-03

1998-12-08

Thomas, Tom

Radiation imagery chemistry: process, composition, or product th

Radiation sensitive product

Silver compound sensitizer containing

438674, 438675, 438667, H01L 23498

Patent

active

058468790

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to semiconductor components having a special contact structure which is provided for vertical, electrically conductive connection of a plurality of semiconductor components. In addition, associated production processes are specified.
2. Description of the Related Art
Semiconductor circuits are produced nowadays using planar technology. The achievable complexity on a chip is limited by its size and the achievable fineness of the structure. The performance of a system comprising a plurality of semiconductor chips connected to one another is considerably limited in the case of conventional technology by the limited number of possible connections between individual chips via connection contacts also referred to as (pads), the low speed of signal transfer via such connections between different chips for example, using an (interface circuit pad/printed circuit board), the limited speed in the case of complex chips due to extensively branched conductor tracks, and the high power consumption of the interface circuits.
These evinced limitations in the use of planar technology can be overcome using three-dimensional interconnection techniques. The arrangement of the functional planes above one another allows parallel communication between these components with a low requirement for electrically conductive connections in one plane, and speed-limiting interchip connections are additionally avoided.
A known process for producing three-dimensional ICs is based on depositing a further semiconductor layer (for example silicon) over a plane of components, recrystallizing the layer using a suitable process (for example local heating by means of a laser) and implementing therein a further component plane. This technique, too, has considerable limitations as a result of the thermal loading of the lower plane during recrystallization and the achievable yield which is limited by defects.
An alternative process from NEC produces the individual component planes separately from one another. These planes are thinned to a few .mu.m and connected to one another by means of wafer bonding. The electrical connections are produced by providing the front and rear sides of the individual component planes with contacts for interchip connection. This process has the following disadvantages and limitations: the thinned wafers must be processed on the front side and on the rear side using technical processes for example, using (lithography with adjustment by the semiconductor wafer). Testing for functionality of the individual planes prior to assembly is made more difficult by the fact that in this process individual components, but not complete circuits, are implemented in each plane. By thinning the wafers right down to the functional elements, SOI-like component structures are produced, with the result that use cannot be made of wafers which have been preproduced using standard technologies (for example standard CMOS).


SUMMARY OF THE INVENTION

An object of the present invention is to provide semiconductor components having a contact structure which is suitable for three-dimensional contact-making, is easy to produce and is improved in comparison with previous interconnections, and associated production processes.
This and other objects and advantages of the invention are achieved by means of the semiconductor components having a contact structure in which a vertical contact with further semiconductor components is formed, the components having a substrate which has a layer structure on a top side and at least one metal pin which penetrates the substrate perpendicularly with respect to the top side, the metal pin being in electrical contact with at least one contact layer made of semiconductor material or a metallic conductor track or a metal contact on the top side, the metal pin touching the contact layer, the conductor track or the metal contact, or the conductor track or the metal contact being fitted to one end of the metal pin, and the metal pin pro

REFERENCES:
patent: 4394712 (1983-07-01), Anthony
patent: 5574311 (1996-11-01), Matsuda

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