Contact structure for interconnection in semiconductor devices a

Details Contact structure for interconnection in semiconductor devices a Contact structure for interconnection in semiconductor devices a

1992-05-26

1994-05-03

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257774, 257740, 257750, 257751, 257754, 437189, 437190, 437203, H01L 2348, H01L 2144

Patent

active

053090233

ABSTRACT:
A contact structure for interconnection in semiconductor devices provides electrical contact between an impurity-diffused region formed in a silicon substrate and a polycrystalline silicon layer through a contact hole. The contact structure for interconnection comprises the silicon substrate, the impurity-diffused region, an insulating oxide film, the interconnection layer formed of a polycrystalline silicon layer containing impurities. The impurity-diffused region is formed in a main surface of the silicon substrate as a source/drain region of an MOS transistor. The insulating oxide film has a contact hole formed therethrough to reach a surface of this impurity-diffused region. A sidewall layer of polycrystalline silicon is formed on the bottom peripheral edge of the contact hole. The interconnection layer is formed on the sidewall layer of polycrystalline silicon and over the insulating oxide film to get contact with the surface of the impurity-diffused region exposed by the contact hole. When the impurities are thermally diffused to make electrical contact between the polycrystalline silicon layer constituting the interconnection layer and the impurity-diffused region, the size of the impurity-diffused region for contact can be controlled such that it does not become larger than that of the contact hole. Thus, the impurity-diffused region for contact can be prevented from adversely affecting characteristics of the MOS transistor.

REFERENCES:
patent: 4507853 (1985-04-01), McDavid
patent: 4967254 (1990-10-01), Shimura
patent: 4967259 (1990-10-01), Takagi
IBM Tech. Bul.-vol. 30, No. 8, Jan. 1988, pp. 295-296.
Ito-Patent Abstracts of Japan, E-881, Jan. 1990 vol. 14, No. 51.

Affiliated with

Also associated with

Rating

Contact structure for interconnection in semiconductor devices a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Contact structure for interconnection in semiconductor devices a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Contact structure for interconnection in semiconductor devices a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2116596