Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-10-25
2003-06-17
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S720000, C438S723000, C257S692000, C257S693000, C257S738000
Reexamination Certificate
active
06579804
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a contact structure and a production method thereof and a probe contact assembly using the contact structure, and more particularly, to a contact structure having a large number of contactors in a vertical direction and to a method for producing such a large number of contactors on a semiconductor wafer in a horizonal direction and removing the contactors from the wafer to be mounted on a substrate in a vertical direction to form the contact structure such as a contact probe assembly, probe card, IC chip, or other contact mechanism.
BACKGROUND OF THE INVENTION
In testing high density and high speed electrical devices such as LSI and VLSI circuits, a high performance contact structure such as a probe card having a large number of contactors must be used. In other applications, contact structures may be used for IC packages as IC leads. The present invention is directed to a production process of such contact structures to be used in testing LSI and VLSI chips, semiconductor wafers, burn-in of semiconductor wafers and die, testing and burn-in of packaged semiconductor devices, printed circuit boards and the like. The present invention can also be applicable to other purposes such as forming leads or terminal pins of IC chips, IC packages or other electronic devices. However, for the convenience of explanation, the present invention is described mainly with reference to the semiconductor wafer testing.
In the case where semiconductor devices to be tested are in the form of a semiconductor wafer, a semiconductor test system such as an IC tester is usually connected to a substrate handler, such as an automatic wafer prober, to automatically test the semiconductor wafer. Such an example is shown in
FIG. 1
in which a semiconductor test system has a test head
100
which is ordinarily in a separate housing and electrically connected to the test system with a bundle of cables
110
. The test head
100
and a substrate handler
400
are mechanically as well as electrically connected with one another with the aid of a manipulator
500
which is driven by a motor
510
. The semiconductor wafers to be tested are automatically provided to a test position of the test head
100
by the substrate handler
400
.
On the test head
100
, the semiconductor wafer to be tested is provided with test signals generated by the semiconductor test system. The resultant output signals from the semiconductor wafer under test (IC circuits formed on the semiconductor wafer) are transmitted to the semiconductor test system. In the semiconductor test system, the output signals are compared with expected data to determine whether the IC circuits on the semiconductor wafer function correctly.
In
FIG. 1
, the test head
100
and the substrate handler
400
are connected through an interface component
140
consisting of a performance board
120
(shown in
FIG. 2
) which is a printed circuit board having electric circuit connections unique to a test head's electrical footprint, coaxial cables, pogo-pins and connectors. In
FIG. 2
, the test head
100
includes a large number of printed circuit boards
150
which correspond to the number of test channels (test pins) of the semiconductor test system. Each of the printed circuit boards
150
has a connector
160
to receive a corresponding contact terminal
121
of the performance board
120
. A “frog” ring
130
is mounted on the performance board
120
to accurately determine the contact position relative to the substrate handler
400
. The frog ring
130
has a large number of contact pins
141
, such as ZIF connectors or pogo-pins, connected to contact terminals
121
, through coaxial cables
124
.
As shown in
FIG. 2
, the test head
100
is placed over the substrate handler
400
and mechanically and electrically connected to the substrate handler through the interface component
140
. In the substrate handler
400
, a semiconductor wafer
300
to be tested is mounted on a chuck
180
. In this example, a probe card
170
is provided above the semiconductor wafer
300
to be tested. The probe card
170
has a large number of probe contactors (such as cantilevers or needles)
190
to contact with contact targets such as circuit terminals or contact pads in the IC circuit on the semiconductor wafer
300
under test.
Electrical terminals or contact receptacles (contact pads) of the probe card
170
are electrically connected to the contact pins
141
provided on the frog ring
130
. The contact pins
141
are also connected to the contact terminals
121
of the performance board
120
with the coaxial cables
124
where each contact terminal
121
is connected to the printed circuit board
150
of the test head
100
. Further, the printed circuit boards
150
are connected to the semiconductor test system through the cable
110
having, for example, several hundreds of inner cables.
Under this arrangement, the probe contactors
190
contact the surface (contact target) of the semiconductor wafer
300
on the chuck
180
to apply test signals to the semiconductor wafer
300
and receive the resultant output signals from the wafer
300
. The resultant output signals from the semiconductor wafer
300
under test are compared with the expected data generated by the semiconductor test system to determine whether the IC circuits on the semiconductor wafer
300
performs properly.
FIG. 3
is a bottom view of the probe card
170
of FIG.
2
. In this example, the probe card
170
has an epoxy ring on which a plurality of probe contactors
190
called needles or cantilevers are mounted. When the chuck
180
mounting the semiconductor wafer
300
moves upward in FIG.
2
, the tips of the cantilevers
190
contact the pads or bumps (contact targets) on the wafer
300
. The ends of the cantilevers
190
are connected to wires
194
which are further connected to transmission lines (not shown) formed in the probe card
170
. The transmission lines are connected to a plurality of electrodes (contact pads)
197
which are in communication with the pogo pins
141
of FIG.
2
.
Typically, the probe card
170
is structured by a multi-layer of polyimide substrates having ground planes, power planes, signal transmission lines on many layers. As is well known in the art, each of the signal transmission lines is designed to have a characteristic impedance such as 50 ohms by balancing the distributed parameters, i.e., dielectric constant and magnetic permeability of the polyimide, inductances and capacitances of the signal paths within the probe card
170
. Thus, the signal lines are impedance matched lines establishing a high frequency transmission bandwidth to the wafer
300
for supplying currents in a steady state as well as high current peaks generated by the device's outputs switching in a transient state. For removing noise, capacitors
193
and
195
are provided on the probe card between the power and ground planes.
An equivalent circuit of the probe card
170
is shown in
FIG. 4
to explain the limitation of the high frequency performance in the conventional probe card technology. As shown in
FIGS. 4A and 4B
, the signal transmission line on the probe card
170
extends from the electrode
197
, the strip (impedance matched) line
196
, the wire
194
and the needle or cantilever (contact structure)
190
. Since the wire
194
and needle
190
are not impedance matched, these portions function as an inductor L in the high frequency band as shown in FIG.
4
C. Because of the overall length of the wire
194
and needle
190
is around 20-30 mm, significant limitations will be resulted from the inductor when testing a high frequency performance of a device under test.
Other factors which limit the frequency bandwidth in the probe card
170
reside in the power and ground needles shown in
FIGS. 4D and 4E
. If the power line can provide large enough currents to the device under test, it will not seriously limit the operational bandwidth in testing the device. However, because the series connected wire
194
and needl
Aldaz Robert Edward
Khoury Theodore A.
Yu David
Zhou Yu
Advantest Corp.
Deo Duy Vu
Muramatsu & Associates
Utech Benjamin L.
LandOfFree
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